| Razor: A low-power pipeline based on circuit-level timing speculation D Ernst, NS Kim, S Das, S Pant, R Rao, T Pham, C Ziesler, D Blaauw, ... Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003 | 1776 | 2003 |
| RazorII: In situ error detection and correction for PVT and SER tolerance S Das, C Tokunaga, S Pant, WH Ma, S Kalaiselvan, K Lai, DM Bull, ... IEEE Journal of Solid-State Circuits 44 (1), 32-48, 2008 | 756 | 2008 |
| A self-tuning DVS processor using delay-error detection and correction S Das, D Roberts, S Lee, S Pant, D Blaauw, T Austin, K Flautner, T Mudge IEEE Journal of Solid-State Circuits 41 (4), 792-804, 2006 | 582 | 2006 |
| Razor: circuit-level correction of timing errors for low-power operation D Ernst, S Das, S Lee, D Blaauw, T Austin, T Mudge, NS Kim, K Flautner IEEE Micro 24 (6), 10-20, 2004 | 544 | 2004 |
| Razor II: In situ error detection and correction for PVT and SER tolerance D Blaauw, S Kalaiselvan, K Lai, WH Ma, S Pant, C Tokunaga, S Das, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 280 | 2008 |
| A power-efficient 32 bit ARM processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation D Bull, S Das, K Shivashankar, GS Dasika, K Flautner, D Blaauw IEEE Journal of Solid-State Circuits 46 (1), 18-31, 2011 | 269* | 2011 |
| A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation (vol 46, pg 18, 2011) D Bull, S Das, K Shivashankar, GS Dasika, K Flautner, D Blaauw IEEE JOURNAL OF SOLID-STATE CIRCUITS 46 (3), 705-705, 2011 | 203* | 2011 |
| Harnessing voltage margins for energy efficiency in multicore CPUs G Papadimitriou, M Kaliorakis, A Chatzidimitriou, D Gizopoulos, ... Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 100 | 2017 |
| A triple core lock-step (TCLS) ARM® Cortex®-R5 processor for safety-critical and ultra-reliable applications X Iturbe, B Venu, E Ozer, S Das 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems …, 2016 | 79 | 2016 |
| Circuit-level timing error tolerance for low-power DSP filters and transforms PN Whatmough, S Das, DM Bull, I Darwazeh IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (6), 989-999, 2013 | 69 | 2013 |
| Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm D Prasad, SST Nibhanupudi, S Das, O Zografos, B Chehab, S Sarkar, ... 2019 IEEE International Electron Devices Meeting (IEDM), 19.1. 1-19.1. 4, 2019 | 67 | 2019 |
| A low-power 1-ghz razor fir accelerator with time-borrow tracking pipeline and approximate error correction in 65-nm cmos PN Whatmough, S Das, DM Bull IEEE Journal of Solid-State Circuits 49 (1), 84-94, 2014 | 54 | 2014 |
| A low-power 1-ghz razor fir accelerator with time-borrow tracking pipeline and approximate error correction in 65-nm cmos PN Whatmough, S Das, DM Bull IEEE Journal of Solid-State Circuits 49 (1), 84-94, 2014 | 54 | 2014 |
| Reducing pipeline energy demands with local DVS and dynamic retiming S Lee, S Das, T Pham, T Austin, D Blaauw, T Mudge Proceedings of the 2004 international symposium on Low power electronics and …, 2004 | 49 | 2004 |
| Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS S Das, P Whatmough, D Bull 2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015 | 47 | 2015 |
| Applications of computation-in-memory architectures based on memristive devices S Hamdioui, HA Du Nguyen, M Taouil, A Sebastian, M Le Gallo, S Pande, ... 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 486-491, 2019 | 42 | 2019 |
| Artificial neural network S Das, R Holm US Patent App. 16/315,991, 2019 | 40 | 2019 |
| Real-Power Computing R Shafik, A Yakovlev, S Das IEEE Transactions on Computers, 2018 | 39 | 2018 |
| Single event upset error detection within an integrated circuit S Das, DT Blaauw, DM Bull US Patent 8,185,812, 2012 | 38 | 2012 |
| Significance-Driven Logic Compression for Energy-Efficient Multiplier Design I Qiqieh, R Shafik, G Tarawneh, D Sokolov, S Das, A Yakovlev IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2018 | 36 | 2018 |
David BlaauwProfessor of Electrical Engineering and Computer Science, University of Michigan在 umich.edu 的电子邮件经过验证
