| An asynchronous power aware and adaptive NoC based circuit E Beigné, F Clermidy, H Lhermet, S Miermont, Y Thonnart, XT Tran, ... Solid-State Circuits, IEEE Journal of 44 (4), 1167-1177, 2009 | 165 | 2009 |
| AES datapath optimization strategies for low-power low-energy multisecurity-level internet-of-things applications DH Bui, D Puschini, S Bacles-Min, E Beigné, XT Tran IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (12 …, 2017 | 91 | 2017 |
| A review of algorithms and hardware implementations for spiking neural networks DA Nguyen, XT Tran, F Iacopi Journal of Low Power Electronics and Applications 11 (2), 23, 2021 | 41 | 2021 |
| Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications DH Bui, D Puschini, S Bacles-Min, E Beigné, XT Tran 2016 International Conference on IC Design and Technology (ICICDT), 1-4, 2016 | 32 | 2016 |
| A DFT architecture for asynchronous networks-on-chip XT Tran, J Durupt, F Bertrand, V Beroulle, C Robach Test Symposium, 2006. ETS'06. Eleventh IEEE European, 219-224, 2006 | 29 | 2006 |
| Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application XT Tran, Y Thonnart, J Durupt, V Beroulle, C Robach Computers & Digital Techniques, IET 3 (5), 487-500, 2009 | 28 | 2009 |
| A design-for-test implementation of an asynchronous network-on-chip architecture and its associated test pattern generation and application XT Tran, Y Thonnart, J Durupt, V Beroulle, C Robach Networks-on-Chip, 2008. NoCS 2008. Second ACM/IEEE International Symposium …, 2008 | 25 | 2008 |
| Soft-Error Resilient 3D Network-on-Chip Router KN Dang, M Meyer, Y Okuyama, AB Abdallah, XT Tran | 21 | 2015 |
| A novel hardware architecture for human detection using HOG-SVM co-optimization ND Nguyen, DH Bui, XT Tran 2019 IEEE Asia Pacific conference on circuits and systems (APCCAS), 33-36, 2019 | 20 | 2019 |
| An efficient Context Adaptive Variable Length coding architecture for H. 264/AVC video encoders NM Nguyen, XT Tran, P Vivet, S Lesecq The 2012 International Conference on Advanced Technologies for …, 2012 | 19* | 2012 |
| TSV-OCT: A scalable online multiple-TSV defects localization for real-time 3-D-IC systems KN Dang, AB Ahmed, AB Abdallah, XT Tran IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (3), 672-685, 2019 | 18 | 2019 |
| FPGA-based lightweight hardware architecture of the PHOTON hash function for IoT edge devices MOA Al-Shatari, FA Hussin, A Abd Aziz, G Witjaksono, XT Tran IEEE access 8, 207610-207618, 2020 | 17 | 2020 |
| An efficient implementation of LED block cipher on FPGA M Al-Shatari, FA Hussin, A Abd Aziz, G Witjaksono, MS Rohmad, XT Tran 2019 First International Conference of Intelligent Computing and Engineering …, 2019 | 17 | 2019 |
| An energy efficient aes encryption core for hardware security implementation in iot systems MH Dao, VP Hoang, VL Dao, XT Tran 2018 International Conference on Advanced Technologies for Communications …, 2018 | 17 | 2018 |
| A comprehensive reliability assessment of fault-resilient network-on-chip using analytical model KN Dang, AB Ahmed, XT Tran, Y Okuyama, AB Abdallah IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (11 …, 2017 | 17 | 2017 |
| A wideband high efficiency Ka-band MMIC power amplifier for 5G wireless communications DP Nguyen, XT Tran, NLK Nguyen, PT Nguyen, AV Pham 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 16 | 2019 |
| A novel reconfigurable router for QoS guarantees in real-time NoC-based MPSoCs HK Nguyen, XT Tran Journal of Systems Architecture 100, 101664, 2019 | 15 | 2019 |
| An efficient hardware implementation of artificial neural network based on stochastic computing DA Nguyen, HH Ho, DH Bui, XT Tran 2018 5th NAFOSTED Conference on Information and Computer Science (NICS), 237-242, 2018 | 15 | 2018 |
| FPGA implementation of a low latency and high throughput network-on-chip router architecture NK Dang, TV Le Van, XT Tran | 15 | 2011 |
| A new data layout scheme for energy-efficient MapReduce processing tasks XT Tran, TV Do, C Rotter, D Hwang Journal of grid computing 16, 285-298, 2018 | 14 | 2018 |
Duy-Hieu BuiVNU Information Technology Institute在 vnu.edu.vn 的电子邮件经过验证
