| A 2 GHz synthesized fractional-N ADPLL with dual-referenced interpolating TDC S Kim, S Hong, K Chang, H Ju, J Shin, B Kim, HJ Park, JY Sim IEEE Journal of Solid-State Circuits 51 (2), 391-400, 2015 | 32 | 2015 |
| A 250- 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications S Hong, S Kim, S Choi, H Cho, J Hong, YH Seo, B Kim, HJ Park, JY Sim IEEE Transactions on Circuits and Systems II: Express Briefs 64 (2), 106-110, 2016 | 10 | 2016 |
| Injection locked digital frequency synthesizer circuit JY Sim, SH Hong US Patent 9,673,827, 2017 | 5 | 2017 |
| A reflection and crosstalk canceling continuous-time linear equalizer for high-speed DDR SDRAM S Hong, CH Bae, YC Sung, J Kim, J Yoon, S Kim, J Baek, C Cho, U Shin, ... 2021 Symposium on VLSI Circuits, 1-2, 2021 | 4 | 2021 |
| 13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process I Choi, S Hong, K Kim, JS Hwang, S Woo, YS Kim, CR Cho, EY Lee, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 234-236, 2024 | 2 | 2024 |
| Receiver for compensating common mode offset S Hong, YC Sung, KIM Wangsoo, S InDal US Patent 11,075,610, 2021 | 1 | 2021 |
