| Refresh control device and semiconductor device including the same DS Kim, JI Kim US Patent 9,818,469, 2017 | 76 | 2017 |
| Memory device and method of refreshing the same J Kim, J Kim, YH Kim, JG Choi, KIM Hee-Seong US Patent 9,646,672, 2017 | 62 | 2017 |
| A 1.0-ns/1.0-V delay-locked loop with racing mode and countered CAS latency controller for DRAM interfaces HW Lee, H Choi, BJ Shin, KH Kim, KW Kim, J Kim, KH Kim, JH Jung, ... IEEE journal of solid-state circuits 47 (6), 1436-1447, 2012 | 38 | 2012 |
| Refresh control device DS Kim, JI Kim US Patent 9,928,896, 2018 | 34 | 2018 |
| 23.2 a 1.1 V 1ynm 6.4 Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, high-speed SerDes and RX/TX equalization scheme D Kim, M Park, S Jang, JY Song, H Chi, G Choi, S Choi, J Kim, C Kim, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 380-382, 2019 | 28 | 2019 |
| Semiconductor memory apparatus and operating method thereof JI Kim US Patent 9,740,556, 2017 | 16 | 2017 |
| Multi-port memory device with serial input/output interface JI Chung, J Kim, CH Do, H Hur US Patent 7,701,800, 2010 | 15 | 2010 |
| Semiconductor device for performing repair operations M su Park, JI Kim US Patent 9,633,750, 2017 | 14 | 2017 |
| Dual edge-triggered flip-flop with modified NAND keeper for high-performance VLSI JI Kim, BS Kong Current Applied Physics 4 (1), 49-53, 2004 | 11 | 2004 |
| Semiconductor apparatus capable of self-tuning a timing margin SA Hyun, JI Kim US Patent 9,373,374, 2016 | 10 | 2016 |
| Pipe latch circuit and driving method thereof J Kim US Patent 8,742,812, 2014 | 10 | 2014 |
| Read operation of multi-port memory device J Kim, CH Do, JI Chung, JH Im US Patent 7,660,168, 2010 | 10 | 2010 |
| Multi-port memory device with serial input/output interface JI Chung, J Kim, CH Do, H Hur US Patent 8,031,552, 2011 | 9 | 2011 |
| Multi-port memory device H Hur, J Kim US Patent 7,835,219, 2010 | 8 | 2010 |
| 25.3 A 1.35 V 5.0 Gb/s/pin GDDR5M with 5.4 mW standby power and an error-adaptive duty-cycle corrector HW Lee, J Song, SA Hyun, S Baek, Y Lim, J Lee, M Park, H Choi, C Choi, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 7 | 2014 |
| Clock path control circuit and semiconductor memory device using the same J Kim US Patent 7,911,853, 2011 | 7 | 2011 |
| Multi-port memory device J Kim, CH Do US Patent 7,447,095, 2008 | 7 | 2008 |
| High voltage generator and word line driving high voltage generator of memory device J Kim, CH Do US Patent 7,710,193, 2010 | 6 | 2010 |
| Memory device MS Park, J Kim US Patent 9,922,728, 2018 | 5 | 2018 |
| Semiconductor memory device JOO No-Guen, KIM Do-Hong, J Kim US Patent 9,627,096, 2017 | 5 | 2017 |
