| ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap JA Carballo, WTJ Chan, PA Gargini, AB Kahng, S Nath 2014 IEEE 32nd International Conference on Computer Design (ICCD), 139-146, 2014 | 121 | 2014 |
| Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning WTJ Chan, PH Ho, AB Kahng, P Saxena Proceedings of the 2017 ACM on International Symposium on Physical Design, 15-21, 2017 | 103 | 2017 |
| Statistical analysis and modeling for error composition in approximate computation circuits WTJ Chan, AB Kahng, S Kang, R Kumar, J Sartori 2013 IEEE 31st International Conference on Computer Design (ICCD), 47-53, 2013 | 81 | 2013 |
| BEOL stack-aware routability prediction from placement using data mining techniques WTJ Chan, Y Du, AB Kahng, S Nath, K Samadi Computer Design (ICCD), 2016 IEEE 34th International Conference on, 41-48, 2016 | 75 | 2016 |
| Learning-based prediction of embedded memory timing failures during initial floorplan design WTJ Chan, KY Chung, AB Kahng, ND MacDonald, S Nath 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 178-185, 2016 | 38 | 2016 |
| The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap WTJ Chan, AB Kahng, S Nath, I Yamamoto 2014 IEEE 32nd International Conference on Computer Design (ICCD), 153-160, 2014 | 29 | 2014 |
| 3DIC benefit estimation and implementation guidance from 2DIC implementation WTJ Chan, S Nath, AB Kahng, Y Du, K Samadi Proceedings of the 52nd Annual Design Automation Conference, 30, 2015 | 20 | 2015 |
| Impact of adaptive voltage scaling on aging-aware signoff TB Chan, WTJ Chan, AB Kahng Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 …, 2013 | 20 | 2013 |
| Optimizing stochastic circuits for accuracy-energy tradeoffs A Alaghi, WTJ Chan, JP Hayes, AB Kahng, J Li Computer-Aided Design (ICCAD), 2015 IEEE/ACM International Conference on …, 2015 | 18 | 2015 |
| On aging-aware signoff for circuits with adaptive voltage scaling TB Chan, WTJ Chan, AB Kahng IEEE Transactions on Circuits and Systems I: Regular Papers 61 (10), 2920-2930, 2014 | 16 | 2014 |
| Trading Accuracy for Energy in Stochastic Circuit Design A Alaghi, WTJ Chan, JP Hayes, AB Kahng, J Li ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (3), 47, 2017 | 14 | 2017 |
| Revisiting 3DIC Benefit with Multiple Tiers WTJ Chan, AB Kahng, J Li Proceedings of the 18th System Level Interconnect Prediction Workshop on ZZZ, 6, 2016 | 13 | 2016 |
| Human Face Detection and Tracking Device US Patent 8,633,978, 0 | 11* | |
| Methodology for electromigration signoff in the presence of adaptive voltage scaling WTJ Chan, AB Kahng, S Nath System Level Interconnect Prediction (SLIP), 2014 ACM/IEEE International …, 2014 | 10 | 2014 |
| Shooting Parameter Adjustment Method for Face Detection and Image Capturing Device for Face Detection US Patent 8,390,736, 0 | 8* | |
| Driving early physical synthesis exploration through end-of-flow total power prediction YC Lu, WT Chan, V Khandelwal, SK Lim Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 97-102, 2022 | 5 | 2022 |
| Predictor-guided cell spreader to improve routability for designs at advanced process nodes P Saxena, WT Chan, PH Ho US Patent 11,194,949, 2021 | 3 | 2021 |
| RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning YC Lu, WT Chan, D Guo, S Kundu, V Khandelwal, SK Lim 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 2 | 2023 |
| Machine learning-based algorithm to accurately predict detail-route DRVS for efficient design closure at advanced technology nodes WT Chan, S Nath, V Khandelwal US Patent 11,636,388, 2023 | 2 | 2023 |
| ILP-Based Identification of Redundant Logic Insertions for Opportunistic Yield Improvement during Early Process Learning TB Chan, WTJ Chan, AB Kahng 2017 IEEE 35th International Conference on Computer Design (ICCD), 269-272, 2017 | 1 | 2017 |
