| Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation O Kwon, Y Lee, S Hong IEEE Access 10, 114552-114565, 2022 | 6 | 2022 |
| Proactively invalidating dead blocks to enable fast writes in STT-MRAM caches Y Kim, Y Chen, Y Lee, L Peng, S Hong IEEE Access 10, 29419-29431, 2022 | 3 | 2022 |
| Rethinking page table structure for fast address translation in gpus: A fixed-size hashed page table S Jang, J Park, O Kwon, Y Lee, S Hong Proceedings of the 2024 International Conference on Parallel Architectures …, 2024 | 2 | 2024 |
| Virtual PTE Storage: Repurposing Last-level Cache to Accelerate Address Translation for Big Data Workloads O Kwon, Y Lee, S Hong 2022 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia), 1-5, 2022 | 1 | 2022 |
| Performance Characterization of CXL Memory Expander: Impact on Read and Write Latencies J Park, W Lee, T Kim, Y Lee, S Hong 2024 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia), 1-5, 2024 | | 2024 |
| Distributed Page Table: Harnessing Physical Memory as an Unbounded Hashed Page Table O Kwon, Y Lee, J Park, S Jang, B Tak, S Hong 2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO), 36-49, 2024 | | 2024 |
| A Case for Speculative Address Translation with Rapid Validation for GPUs J Park, O Kwon, Y Lee, S Kim, G Byeon, J Yoon, PJ Nair, S Hong 2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO), 278-292, 2024 | | 2024 |
| Don't open row: rethinking row buffer policy for improving performance of non-volatile memories Y Lee, O Kwon, S Hong Proceedings of the 59th ACM/IEEE Design Automation Conference, 823-828, 2022 | | 2022 |
