| Built-in test for VLSI: pseudorandom techniques PH Bardell, WH McAnney, J Savir Wiley-Interscience, 1987 | 1657 | 1987 |
| Broad-side delay test J Savir, S Patil IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994 | 526 | 1994 |
| Random pattern testability J Savir, GS Ditlow, PH Bardell IEEE Transactions on Computers 100 (1), 79-90, 1984 | 368 | 1984 |
| Syndrome-testable design of combinational circuits Savir IEEE Transactions on Computers 100 (6), 442-451, 1980 | 297 | 1980 |
| Scan-based transition test J Savir, S Patil IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993 | 248 | 1993 |
| Skewed-load transition test: Part I, calculus J Savir Proceedings International Test Conference 1992, 705-705, 1992 | 242 | 1992 |
| Random pattern testability of delay faults J Savir, WH Mcanney IEEE transactions on computers 37 (3), 291-300, 1988 | 135 | 1988 |
| Skewed-load transition test: part II, coverage S Patil, J Savir Proceedings International Test Conference 1992, 714-714, 1992 | 130 | 1992 |
| On random pattern test length Savir, Bardell IEEE Transactions on Computers 100 (6), 467-474, 1984 | 130 | 1984 |
| THERE IS INFORMATION IN FAULTY SIGNATURES. WH McAnney, J Savir Dig Pap Int Test Conf 1987, Proc, Integr of Test with Des and Manuf, 630-636, 1987 | 104 | 1987 |
| The weighted syndrome sums approach to VLSI testing Barzilai, Savir, Markowsky IEEE transactions on Computers 100 (12), 996-1000, 1981 | 83 | 1981 |
| Identification of failing tests with cycling registers J Savir, WH McAnney International Test Conference 1988 Proceeding@ m_New Frontiers in Testing …, 1988 | 82 | 1988 |
| A multiple seed linear feedback shift register J Savir, WH McAnney Proceedings. International Test Conference 1990, 657-659, 1990 | 81 | 1990 |
| Good controllability and observability do not guarantee good testability Savir IEEE Transactions on computers 100 (12), 1198-1200, 1983 | 76 | 1983 |
| Coefficient-based test of parametric faults in analog circuits Z Guo, J Savir IEEE Transactions on Instrumentation and Measurement 55 (1), 150-157, 2006 | 72 | 2006 |
| Scan-based delay tests having enhanced test vector pattern generation J Savir US Patent 5,642,362, 1997 | 67 | 1997 |
| Test limitations of parametric faults in analog circuits J Savir, Z Guo IEEE Transactions on Instrumentation and Measurement 52 (5), 1444-1454, 2003 | 61 | 2003 |
| At-speed test is not necessarily an AC test J Savir, R Berry Digest of Papers-International Test Conference, 722-728, 1992 | 58 | 1992 |
| Universal weight generator J Savir US Patent 5,394,405, 1995 | 51 | 1995 |
| TESTING FOR, AND DISTINGUISHING BETWEEN FAILURES. J Savir, JP Roth | 50 | 1982 |
