| A novel stereovision algorithm for obstacles detection based on UV-disparity approach I Benacer, A Hamissi, A Khouas 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 369-372, 2015 | 16 | 2015 |
| A fast systolic priority queue architecture for a flow-based Traffic Manager I Benacer, FR Boyer, N Bélanger, Y Savaria 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 1-4, 2016 | 14 | 2016 |
| A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue I Benacer, FR Boyer, Y Savaria IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (10 …, 2018 | 13 | 2018 |
| A high-speed traffic manager architecture for flow-based networking I Benacer, FR Boyer, Y Savaria 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS …, 2017 | 10 | 2017 |
| A High-Speed, Scalable and Programmable, Traffic Manager Architecture for Flow-Based Networking I Benacer, FR Boyer, Y Savaria IEEE Access, 2018 | 7 | 2018 |
| Design of a low latency 40 Gb/s flow-based traffic manager using high-level synthesis I Benacer, FR Boyer, Y Savaria 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 7 | 2018 |
| HPQ: a High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches I Benacer, FR Boyer, Y Savaria New Circuits and Systems Conference (NEWCAS), 2018 16th IEEE International, 2018 | 6 | 2018 |
| HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices I Benacer, FR Boyer, Y Savaria IEEE Access 7, 130672-130684, 2019 | 4 | 2019 |
| Hardware design and FPGA implementation for road plane extraction based on V-disparity approach I Benacer, A Hamissi, A Khouas 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2053-2056, 2015 | 3 | 2015 |
| Fast, Scalable, and Flexible C++ Hardware Architectures for Network Data Plane Queuing and Traffic Management I Benacer Polytechnique Montréal, 2019 | | 2019 |
