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Xiang Feng
Xiang Feng
chip design engineer, hisilicon, Huawei
在 hisilicon.com 的电子邮件经过验证
标题
引用次数
引用次数
年份
RLWE-oriented high-speed polynomial multiplier utilizing multi-lane stockham NTT algorithm
X Feng, S Li, S Xu
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (3), 556-559, 2019
392019
Design of an area-effcient million-bit integer multiplier using double modulus NTT
X Feng, S Li
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (9 …, 2017
292017
Accelerating an FHE integer multiplier using negative wrapped convolution and ping-pong FFT
X Feng, S Li
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (1), 121-125, 2018
242018
A High Performance FPGA Implementation of 256-bit Elliptic Curve Cryptography Processor Over GF(p)
X Feng, S Li
IEICE Transactions on Fundamentals of Electronics, Communications and …, 2015
132015
A high-speed and spa-resistant implementation of ecc point multiplication over gf (p)
X Feng, S Li
2017 IEEE Trustcom/BigDataSE/ICESS, 255-260, 2017
92017
An area-efficient fpga implementation of skinny block cipher for lightweight application
X Feng, S Li
2017 International Conference on Electron Devices and Solid-State Circuits …, 2017
22017
Design of a fast number theoretical transform engine for fully homomorphic encryption
X Feng, S Li
2017 IEEE International Symposium on Consumer Electronics (ISCE), 86-87, 2017
2017
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