| Automated generation of security assertions for rtl models H Witharana, A Jayasena, A Whigham, P Mishra ACM Journal on Emerging Technologies in Computing Systems 19 (1), 1-27, 2023 | 18 | 2023 |
| TVLA*: Test vector leakage assessment on hardware implementations of asymmetric cryptography algorithms A Jayasena, E Andrews, P Mishra IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023 | 7 | 2023 |
| Directed test generation for hardware validation: A survey A Jayasena, P Mishra ACM Computing Surveys 56 (5), 1-36, 2024 | 4 | 2024 |
| Scalable detection of hardware trojans using ATPG-based activation of rare events A Jayasena, P Mishra IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 3 | 2023 |
| Network-on-chip trust validation using security assertions A Jayasena, B Kumar, S Charles, H Witharana, P Mishra Journal of Hardware and Systems Security 6 (3), 79-94, 2022 | 3 | 2022 |
| Efficient finite state machine encoding for defending against laser fault injection attacks A Jayasena, K Rani, P Mishra 2022 IEEE 40th International Conference on Computer Design (ICCD), 247-254, 2022 | 3 | 2022 |
| Network-on-Chip Security and Trust Verification A Jayasena, S Charles, P Mishra Network-on-Chip Security and Privacy, 311-337, 2021 | 2 | 2021 |
| HIVE: Scalable Hardware-Firmware Co-Verification using Scenario-based Decomposition and Automated Hint Extraction A Jayasena, P Mishra IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 1 | 2024 |
| DETER: Design for Trust Utilizing Rareness Reduction A Jayasena, P Mishra arXiv preprint arXiv:2302.08984, 2023 | 1 | 2023 |
| Register transfer level disparity generator with stereo vision A Jayasena Journal of Open Research Software 9 (1), 2021 | 1 | 2021 |
| Incremental Concolic Testing of Register-Transfer Level Designs H Witharana, A Jayasena, P Mishra ACM Transactions on Design Automation of Electronic Systems 29 (5), 1-23, 2024 | | 2024 |
| EvilCS: An Evaluation of Information Leakage through Context Switching on Security Enclaves A Jayasena, R Bachmann, P Mishra 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2024 | | 2024 |
| Information Leakage through Physical Layer Supply Voltage Coupling Vulnerability S Sanjaya, A Jayasena, P Mishra arXiv preprint arXiv:2403.08132, 2024 | | 2024 |
| Design for Trust Utilizing Rareness Reduction A Jayasena, P Mishra 2024 37th International Conference on VLSI Design and 2024 23rd …, 2024 | | 2024 |
| CISELeaks: Information Leakage Assessment of Cryptographic Instruction Set Extension Prototypes A Jayasena, R Bachmann, P Mishra Cryptology ePrint Archive, 2024 | | 2024 |
| Logic Locking based Trojans: A Friend Turns Foe Y Liu, A Jayasena, P Mishra, A Srivastava arXiv preprint arXiv:2309.15067, 2023 | | 2023 |
| Sequence-Based Incremental Concolic Testing of RTL Models H Witharana, A Jayasena, P Mishra arXiv preprint arXiv:2302.12241, 2023 | | 2023 |
Prabhat MishraProfessor, Univ. of Florida, IEEE Fellow, AAAS Fellow, ACM Distinguished Member在 ufl.edu 的电子邮件经过验证
