| A tutorial introduction to research on analog and mixed-signal circuit testing LS Milor IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1998 | 411 | 1998 |
| Detection of catastrophic faults in analog integrated circuits L Milor, V Visvanathan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1989 | 271 | 1989 |
| Minimizing production test time to detect faults in analog circuits L Milor, AL Sangiovanni-Vincentelli IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994 | 237 | 1994 |
| Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits M Orshansky, L Milor, P Chen, K Keutzer, C Hu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002 | 215 | 2002 |
| Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction M Orshansky, L Milor, C Hu IEEE Transactions on Semiconductor Manufacturing 17 (1), 2-11, 2004 | 140 | 2004 |
| Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits M Orshansky, L Milor, P Chen, K Keutzer, C Hu IEEE/ACM International Conference on Computer Aided Design. ICCAD-2000. IEEE …, 2000 | 116 | 2000 |
| Optimal test set design for analog circuits L Milor, A Sangiovanni-Vincentelli 1990 IEEE International Conference on Computer-Aided Design, 294,295,296,297 …, 1990 | 112 | 1990 |
| Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST F Ahmed, L Milor 2010 28th VLSI Test Symposium (VTS), 63-68, 2010 | 59 | 2010 |
| Computing parametric yield accurately and efficiently L Milor, A Sangiovanni-Vincentelli 1990 IEEE International Conference on Computer-Aided Design, 116,117,118,119 …, 1990 | 48 | 1990 |
| Circuit sensitivity to interconnect variation Z Lin, CJ Spanos, LS Milor, YT Lin IEEE Transactions on Semiconductor Manufacturing 11 (4), 557-568, 1998 | 44 | 1998 |
| Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing M Choi, L Milor IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 40 | 2006 |
| Analysis of the impact of proximity correction algorithms on circuit performance L Chen, LS Milor, CH Ouyang, W Maly, YK Peng IEEE Transactions on Semiconductor Manufacturing 12 (3), 313-322, 1999 | 40 | 1999 |
| Yield modeling based on in-line scanner defect sizing and a circuit's critical area LS Milor IEEE transactions on semiconductor manufacturing 12 (1), 26-35, 1999 | 38 | 1999 |
| An analytical model of multiple ILD thickness variation induced by interaction of layout pattern and CMP process C Ouyang, K Ryu, L Milor, W Maly, G Hill, YK Peng IEEE transactions on semiconductor manufacturing 13 (3), 286-292, 2000 | 37 | 2000 |
| System-level modeling of microprocessor reliability degradation due to BTI and HCI CC Chen, S Cha, T Liu, L Milor 2014 IEEE International Reliability Physics Symposium, CA. 8.1-CA. 8.9, 2014 | 34 | 2014 |
| SRAM stability analysis for different cache configurations due to bias temperature instability and hot carrier injection T Liu, CC Chen, J Wu, L Milor 2016 IEEE 34th International Conference on Computer Design (ICCD), 225-232, 2016 | 32 | 2016 |
| Performance modeling using additive regression splines CY Chao, LS Milor IEEE transactions on semiconductor manufacturing 8 (3), 239-251, 1995 | 30 | 1995 |
| Backend low-k TDDB chip reliability simulator M Bashir, DH Kim, K Athikulwongse, SK Lim, L Milor 2011 International Reliability Physics Symposium, 2C. 2.1-2C. 2.10, 2011 | 29 | 2011 |
| System-level modeling and microprocessor reliability analysis for backend wearout mechanisms CC Chen, L Milor 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 28 | 2013 |
| A DLL design for testing I/O setup and hold times C Jia, L Milor IEEE transactions on very large scale integration (VLSI) systems 17 (11 …, 2009 | 28 | 2009 |
