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Ajinkya Kale
Ajinkya Kale
Silicon Austria Labs
在 silicon-austria.com 的电子邮件经过验证
标题
引用次数
引用次数
年份
A− 40 dB EVM, 77 MHz dual-band tunable gain sub-sampling receiver front end in 65-nm CMOS
A Kale, S Popuri, M Koeberle, J Sturm, VSR Pasupureddi
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (3), 1166-1179, 2018
242018
Wideband channelized sub-sampling transceiver for digital RF memory based electronic attack system
A Kale, R Thirumuru, VSR Pasupureddi
Aerospace Science and Technology 51, 34-41, 2016
122016
Wireless sensor network hardware platforms and multi-channel communication protocols: A survey
M Karani, A Kale, A Kopekar
Proceedings on 2nd National Conference on Information and Communication …, 2011
112011
A Double-Balanced N-phase Passive 3× Sub-Harmonic Down-Conversion Mixer
M Akula, A Kale, J Sturm
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021
82021
A half-rate built-in self-test for high-speed serial interface using a PRBS generator and checker
RRR Bodha, S Sarafi, A Kale, M Koberle, J Sturm
2019 Austrochip Workshop on Microelectronics (Austrochip), 43-46, 2019
72019
Integration solutions for reconfigurable multi-standard wireless transceivers
A Kale, G Batistell, S Popuri, VSR Pasupureddi, W Bösch, J Sturm
e & i Elektrotechnik und Informationstechnik 135 (1), 18-23, 2018
62018
Design and simulation of a wideband channelized transceiver for DRFM applications
A Kale, PVS Rao, J Chattopadhyay
2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 635-638, 2014
42014
SCPA non-linearity Modelling and Analysis
G Batistell, A Kale, J Sturm, W Bösch
2018 International Workshop on Integrated Nonlinear Microwave and Millimetre …, 2018
32018
Performance Evaluation of Routing Algorithms for Ad Hoc Wireless Sensor Network and Enhancing the Parameters for Good Throughput
AS Kopekar, AS Dhakate, A Kale
International journal of applied information systems (IJAIS) 3 (6), 23-8, 2012
32012
0.9 to 2.5 GHz Sub-Sampling Receiver Architecture for Dynamically Reconfigurable SDR
A Kale, J Sturm, VSR Pasupureddi
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 316-320, 2018
22018
Analysis of Common-Mode Isolation on Transformer Based Balun
G Batistell, SM Mahani, S Popuri, A Kale, J Sturm, W Bösch
2019 Austrochip Workshop on Microelectronics (Austrochip), 71-75, 2019
12019
A− 40‐dB EVM 20‐MHz subsampling multistandard receiver architecture with dynamic carrier detection, bandwidth estimation, and EVM optimization
A Kale, J Sturm, VSR Pasupureddi
International Journal of Circuit Theory and Applications 47 (4), 549-560, 2019
12019
An On-Chip Analog Spectrum Analyzer Based on Miller Frequency Divider
AH Marangalou, SM Sondon, A Kale, J Sturm, M Gadringer, W Bösch
2020 Austrochip Workshop on Microelectronics (Austrochip), 90-94, 2020
2020
Subsampling CMOS Frontends for Multistandard Reconfigurable RF Radios
AU KALE
International Institute of Information Technology, 2018
2018
Integrationskonzepte für konfigurierbare Multi-Standard-Drahtlos-Transceiver
A Kale, G Batistell, S Popuri, VSR Pasupureddi, W Bösch, J Sturm
Elektrotechnik und Informationstechnik 135 (1), 18-23, 2018
2018
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