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Ashish Panchal
Ashish Panchal
IET DAVV Indore
在 ietdavv.edu.in 的电子邮件经过验证
标题
引用次数
引用次数
年份
Improved reliability single loop single feed 7T SRAM cell for biomedical applications
A Panchal, P Sharma, A Gupta, V Neema, N Tiwari, R Sindal
Memories-Materials, Devices, Circuits and Systems 4, 100057, 2023
92023
Methods for noise margin analysis of conventional 6 T and 8 T SRAM cell
A Gupta, R Sindal, P Sharma, A Panchal, V Neema
Materials Today: Proceedings, 2023
52023
Proposed approximate hybrid memory architecture for handheld multimedia devices
P Sharma, V Neema, A Panchal
Materials Today: Proceedings, 2023
52023
A Novel approach to design secure and reliable SRAM from power analysis attack using power equalizer circuit
P Sharma, A Gupta, A Panchal, V Neema
2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2024
22024
Comparative study of decoupled read buffer SRAM memory cell for improve read noise margin
A Panchal, N Tiwari, P Sharma
Materials Today: Proceedings, 2023
22023
FPGA implementation of proposed number plate localization algorithm based on YOLOv2 (You Only Look Once)
V Panchal, H Sankla, P Sharma, V Neema, A Panchal, SS Chouhan
Microsystem Technologies 29 (10), 1501-1513, 2023
12023
Secure Embedded SRAM from Side Channel and Data Imprinting Attacks
A Gupta, R Sindal, V Neema, A Panchal
International Conference on Security, Surveillance and Artificial …, 2024
2024
Optimal Implementation of 6T SRAM using 0.12 µm NWL CMOS Technology
A Panchal, D Kishore, R Sharma
2013
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