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Ivan Vargas-Valdivieso
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Vitruvius+: An area-efficient RISC-V decoupled vector coprocessor for high performance computing applications
F Minervini Minervini, Ó Palomar Pérez, OS Unsal, E Reggiani, ...
ACM transactions on architecture and code optimization 20 (2, article 28), 1-25, 2023
232023
An academic risc-v silicon implementation based on open-source components
J Abella, C Bulla, G Cabo, FJ Cazorla, A Cristal, M Doblas, R Figueras, ...
2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS), 1-6, 2020
212020
Via: A smart scratchpad for vector units with application to sparse matrix computations
J Pavón, IV Valdivieso, A Barredo, J Marimon, M Moreto, F Moll, O Unsal, ...
2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021
122021
DVINO: A RISC-V vector processor implemented in 65nm technology
G Cabo, G Candón, X Carril, M Doblas, M Domínguez, A González, ...
2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), 1-6, 2022
62022
VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing
J Pavón, IV Valdivieso, J Marimon, R Figueras, F Moll, O Unsal, M Valero, ...
2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023
12023
Sargantana: an academic SoC RISC-V processor in 22nm FDSOI technology
M Doblas Font, G Candón Arenas, X Carril Gil, M Dominguez de la Rocha, ...
38th Conference on Design of Circuits and Integrated Systems (DCIS 2023 …, 2023
2023
Lagarto: First Silicon RISC-V Academic Processor Developed in Spain
J Abella, G Cabo, FJ Cazorla, A Cristal, R Figueras, A González, ...
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