| Architecture and CAD for deep-submicron FPGAs V Betz, J Rose, A Marquardt Springer Science & Business Media, 2012 | 1808 | 2012 |
| Timing-driven placement for FPGAs A Marquardt, V Betz, J Rose Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field …, 2000 | 368 | 2000 |
| Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density A Marquardt, V Betz, J Rose Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field …, 1999 | 363 | 1999 |
| The Stratix II Logic and Routing Architecture D Lewis, E Ahmed, G Baeckler, V Betz, M Bourgeault, D Cashman, ... Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field …, 2005 | 263 | 2005 |
| The Stratix Routing and Logic Architecture D Lewis, V Betz, D Jefferson, A Lee, C Lane, P Leventis, S Marquardt, ... Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field …, 2003 | 171 | 2003 |
| The Stratix-II Routing and Logic Architecture D Lewis, V Betz, D Jefferson, A Lee, C Lane, P Leventis, S Marquardt, ... Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field …, 2005 | 142 | 2005 |
| Speed and area tradeoffs in cluster-based FPGA architectures A Marquardt, V Betz, J Rose IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (1), 84-93, 2000 | 132 | 2000 |
| Architecture and CAD for deep-submicron FPGAs. Vol. 497 V Betz, J Rose, A Marquardt Cham, Switzerland: Springer, 2012 | 52 | 2012 |
| Versatile logic element and logic array block DM Lewis, P Leventis, AL Lee, H Kim, B Pedersen, C Wysocki, CF Lane, ... US Patent 7,218,133, 2007 | 49 | 2007 |
| Method and system for estimating the reliability of blacklists of botnet-infected computers DO García, JL Garcia, AF Segador, A Marquardt, MV Vilasero US Patent 8,516,595, 2013 | 42 | 2013 |
| Routing architecture for a programmable logic device DM Lewis, P Leventis, AL Lee, BD Johnson, R Cliff, ST Reddy, CF Lane, ... US Patent 6,630,842, 2003 | 27 | 2003 |
| Versatile logic element and logic array block DM Lewis, P Leventis, AL Lee, H Kim, B Pedersen, C Wysocki, CF Lane, ... US Patent 6,937,064, 2005 | 22 | 2005 |
| Cluster-based architecture, timing-driven packing and timing-driven placement for FPGAs. AR Marquardt University of Toronto, 2001 | 20 | 2001 |
| Routing tools and routing architecture generation V Betz, J Rose, A Marquardt, V Betz, J Rose, A Marquardt Architecture and CAD For Deep-Submicron FPGAS, 63-103, 1999 | 11 | 1999 |
| Background and Previous Work V Betz, J Rose, A Marquardt, V Betz, J Rose, A Marquardt Architecture and CAD for Deep-Submicron FPGAS, 11-35, 1999 | 10 | 1999 |
| Global Routing Architecture V Betz, J Rose, A Marquardt, V Betz, J Rose, A Marquardt Architecture and CAD for Deep-Submicron FPGAS, 105-126, 1999 | 9 | 1999 |
| Detailed Routing Architecture V Betz, J Rose, A Marquardt, V Betz, J Rose, A Marquardt Architecture and CAD for Deep-Submicron FPGAS, 151-190, 1999 | 9 | 1999 |
| Architecture and CAD for Deep-Submicron FPGAs. 1999 V Betz, J Rose, A Marquardt Kluwer Academic Publishers, 0 | 8 | |
| Architecture and CAD for Deep-Submicron FPGAs, chapter Appendix B V Betz, J Rose, A Marquardt The Kluwer International Series in Engineering and Computer Science. Kluwer …, 1999 | 3 | 1999 |
| Cluster-Based Logic Blocks V Betz, J Rose, A Marquardt, V Betz, J Rose, A Marquardt Architecture and CAD for Deep-Submicron FPGAS, 127-149, 1999 | 2 | 1999 |
Vaughn BetzUniversity of Toronto在 eecg.utoronto.ca 的电子邮件经过验证
Vaughn BetzUniversity of Toronto在 eecg.utoronto.ca 的电子邮件经过验证
Jonathan RoseProfessor of Electrical and Computer Engineering, University of Toronto在 ece.utoronto.ca 的电子邮件经过验证