| Coverage analysis techniques for hdl design validation JY Jou, CNJ Liu Proc. Asia Pacific CHip Design Languages, 48-55, 1999 | 66 | 1999 |
| Hybrid approach to faster functional verification with full visibility CL Chuang, WH Cheng, DJ Lu, CNJ Liu IEEE Design & Test of Computers 24 (2), 154-162, 2007 | 38 | 2007 |
| A tree-topology multiplexer for multiphase clock system H Lu, C Su, CNJ Liu IEEE Transactions on Circuits and Systems I: Regular Papers 56 (1), 124-131, 2008 | 37 | 2008 |
| Simultaneous optimization of analog circuits with reliability and variability for applications on flexible electronics YL Chen, WR Wu, CNJ Liu, JCM Li IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 30 | 2013 |
| Fast statistical analysis of process variation effects using accurate PLL behavioral models CC Kuo, MJ Lee, CN Liu, CJ Huang IEEE Transactions on Circuits and Systems I: Regular Papers 56 (6), 1160-1172, 2008 | 25 | 2008 |
| An automatic controller extractor for HDL descriptions at the RTL CNJ Liu, JY Jou IEEE Design & Test of Computers 17 (3), 72-77, 2000 | 25 | 2000 |
| Analog placement with current flow and symmetry constraints using PCP-SP A Patyal, PC Pan, HM Chen, HY Chi, CN Liu Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 24 | 2018 |
| LASER: layout-aware analog synthesis environment on laker YC Liao, YL Chen, XT Cai, CN Liu, TC Chen Proceedings of the 23rd ACM international conference on Great lakes …, 2013 | 23 | 2013 |
| Efficient coverage analysis metric for HDL design validation CN Liu, JY Jou IEE Proceedings-Computers and Digital Techniques 148 (1), 1-6, 2001 | 23 | 2001 |
| Accurate rank ordering of error candidates for efficient HDL design debugging TY Jiang, CNJ Liu, JY Jou IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 21 | 2009 |
| Design of an all-digital LVDS driver H Lu, HW Wang, C Su, CNJ Liu IEEE Transactions on Circuits and Systems I: Regular Papers 56 (8), 1635-1644, 2008 | 21 | 2008 |
| Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs TY Jiang, CNJ Liu, JY Jou 2005 IEEE International Symposium on Circuits and Systems (ISCAS), 5682-5685, 2005 | 19 | 2005 |
| Performance-preserved analog routing methodology via wire load reduction HY Chi, HY Tseng, CNJ Liu, HM Chen 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 482-487, 2018 | 18 | 2018 |
| ILP-based inter-die routing for 3D ICs CJ Chang, PJ Huang, TC Chen, CNJ Liu 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 330-335, 2011 | 17 | 2011 |
| A novel approach for functional coverage measurement in HDL CNJ Liu, CY Chang, JY Jou, MC Lai, HM Juan 2000 IEEE International Symposium on Circuits and Systems (ISCAS) 4, 217-220, 2000 | 16 | 2000 |
| Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits YL Chen, W Wu, CNJ Liu, L He The 20th Asia and South Pacific Design Automation Conference, 556-561, 2015 | 15 | 2015 |
| A bias-driven approach to improve the efficiency of automatic design optimization for CMOS OP-Amps YF Cheng, LY Chan, YL Chen, YC Liao, CNJ Liu 2012 4th Asia Symposium on Quality Electronic Design (ASQED), 59-63, 2012 | 15 | 2012 |
| A scalable digitalized buffer for gigabit I/O HW Lu, CC Su, CN Liu 2008 IEEE Custom Integrated Circuits Conference, 241-244, 2008 | 14 | 2008 |
| A novel approach for high-level power modeling of sequential circuits using recurrent neural networks WT Hsieh, CC Shiue, CNJ Liu 2005 IEEE International Symposium on Circuits and Systems (ISCAS), 3591-3594, 2005 | 14 | 2005 |
| A fsm extractor for hdl description at rtl level CN Liu, JY Jou Proc. of Asia-Pacific Conference on Hardware Description Languages, 33-38, 1998 | 13 | 1998 |
