Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory P Chi, S Li, C Xu, T Zhang, J Zhao, Y Liu, Y Wang, Y Xie ACM SIGARCH Computer Architecture News 44 (3), 27-39, 2016 | 1720 | 2016 |
Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory X Dong, C Xu, Y Xie, NP Jouppi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 1328 | 2012 |
Towards artificial general intelligence with hybrid Tianjic chip architecture J Pei, L Deng, S Song, M Zhao, Y Zhang, S Wu, G Wang, Z Zou, Z Wu, ... Nature 572 (7767), 106-111, 2019 | 827 | 2019 |
Model compression and hardware acceleration for neural networks: A comprehensive survey L Deng, G Li, S Han, L Shi, Y Xie Proceedings of the IEEE 108 (4), 485-532, 2020 | 774 | 2020 |
Enhanced pix2pix dehazing network Y Qu, Y Chen, J Huang, Y Xie Proceedings of the IEEE/CVF conference on computer vision and pattern …, 2019 | 666 | 2019 |
Design space exploration for 3D architectures Y Xie, GH Loh, B Black, K Bernstein ACM Journal on Emerging Technologies in Computing Systems (JETC) 2 (2), 65-103, 2006 | 614 | 2006 |
Direct training for spiking neural networks: Faster, larger, better Y Wu, L Deng, G Li, J Zhu, Y Xie, L Shi Proceedings of the AAAI conference on artificial intelligence 33 (01), 1311-1318, 2019 | 608 | 2019 |
Contrastive learning for compact single image dehazing H Wu, Y Qu, S Lin, J Zhou, R Qiao, Z Zhang, Y Xie, L Ma Proceedings of the IEEE/CVF conference on computer vision and pattern …, 2021 | 601 | 2021 |
Design and management of 3D chip multiprocessors using network-in-memory F Li, C Nicopoulos, T Richardson, Y Xie, V Narayanan, M Kandemir ACM SIGARCH Computer Architecture News 34 (2), 130-141, 2006 | 548 | 2006 |
A novel architecture of the 3D stacked MRAM L2 cache for CMPs G Sun, X Dong, Y Xie, J Li, Y Chen 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 538 | 2009 |
Evidence of a Broad Structure at an Invariant Mass of in the Reaction Measured at BABAR B Aubert, R Barate, M Bona, D Boutigny, F Couderc, Y Karyotakis, ... Physical review letters 98 (21), 212001, 2007 | 502 | 2007 |
Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories S Li, C Xu, Q Zou, J Zhao, Y Lu, Y Xie Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 494 | 2016 |
Hybrid cache architecture with disparate memory technologies X Wu, J Li, L Zhang, E Speight, R Rajamony, Y Xie ACM SIGARCH computer architecture news 37 (3), 34-45, 2009 | 482 | 2009 |
Tackling the qubit mapping problem for NISQ-era quantum devices G Li, Y Ding, Y Xie Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019 | 477 | 2019 |
Cambricon: An instruction set architecture for neural networks S Liu, Z Du, J Tao, D Han, T Luo, Y Xie, Y Chen, T Chen ACM SIGARCH Computer Architecture News 44 (3), 393-405, 2016 | 442 | 2016 |
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement X Dong, X Wu, G Sun, Y Xie, H Li, Y Chen Proceedings of the 45th annual design automation conference, 554-559, 2008 | 427 | 2008 |
Drisa: A dram-based reconfigurable in-situ accelerator S Li, D Niu, KT Malladi, H Zheng, B Brennan, Y Xie Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 426 | 2017 |
Processor design in 3D die-stacking technologies GH Loh, Y Xie, B Black Ieee Micro 27 (3), 31-48, 2007 | 423 | 2007 |
DLAU: A scalable deep learning accelerator unit on FPGA C Wang, L Gong, Q Yu, X Li, Y Xie, X Zhou IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 422 | 2016 |
Overcoming the challenges of crossbar resistive memory architectures C Xu, D Niu, N Muralimanohar, R Balasubramonian, T Zhang, S Yu, Y Xie 2015 IEEE 21st international symposium on high performance computer …, 2015 | 396 | 2015 |