| A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector J Savoj, B Razavi IEEE Journal of Solid-State Circuits 36 (5), 761-768, 2001 | 380 | 2001 |
| A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector J Savoj, B Razavi IEEE Journal of Solid-State Circuits 38 (1), 13-21, 2003 | 236 | 2003 |
| High-speed CMOS circuits for optical receivers J Savoj, B Razavi Springer Science & Business Media, 2007 | 110 | 2007 |
| Data receivers and methods of implementing data receivers in an integrated circuit CH Hsieh, KY Chang, J Savoj US Patent 9,325,489, 2016 | 102 | 2016 |
| A 10 Gb/s CMOS clock and data recovery circuit with frequency detection J Savoj, B Razavi 2001 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2001 | 86 | 2001 |
| Receiver with enhanced clock and data recovery HC Lee, B Leibowitz, J Kim, J Savoj US Patent 8,929,496, 2015 | 81 | 2015 |
| 2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS JC Chien, P Upadhyaya, H Jung, S Chen, W Fang, AM Niknejad, J Savoj, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 72 | 2014 |
| A 12-GS/s phase-calibrated CMOS digital-to-analog converter for backplane communications J Savoj, A Abbasfar, A Amirkhany, M Jeeradit, BW Garlepp IEEE Journal of Solid-State Circuits 43 (5), 1207-1216, 2008 | 59 | 2008 |
| 3.3 A 0.5-to-32.75 Gb/s flexible-reach wireline transceiver in 20nm CMOS P Upadhyaya, J Savoj, FT An, A Bekele, A Jose, B Xu, D Wu, D Turker, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 53 | 2015 |
| Nfc device having a differential input envelope detector C Marcu, J Savoj US Patent App. 12/897,520, 2012 | 52 | 2012 |
| A 10-Gb/s CMOS clock and data recovery circuit J Savoj, B Razavi 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No …, 2000 | 48 | 2000 |
| Linear half-rate phase detector and clock and data recovery circuit J Savoj US Patent 7,016,613, 2006 | 47 | 2006 |
| A 24 Gb/s software programmable analog multi-tone transmitter A Amirkhany, A Abbasfar, J Savoj, M Jeeradit, B Garlepp, RT Kollipara, ... IEEE Journal of Solid-State Circuits 43 (4), 999-1009, 2008 | 46 | 2008 |
| Low power LO distribution using a frequency-multiplying subharmonically injection-locked oscillator D Park, J Savoj US Patent 9,374,100, 2016 | 44 | 2016 |
| Design of half-rate clock and data recovery circuits for optical communication systems J Savoj, B Razavi Proceedings of the 38th annual Design Automation Conference, 121-126, 2001 | 40 | 2001 |
| Design of high-speed wireline transceivers for backplane communications in 28nm CMOS J Savoj, K Hsieh, P Upadhyaya, FT An, J Im, X Jiang, J Kamali, KW Lai, ... Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012 | 38 | 2012 |
| A 0.5–16.3 Gb/s fully adaptive flexible-reach transceiver for FPGA in 20 nm CMOS Y Frans, D Carey, M Erett, H Amir-Aslanzadeh, WY Fang, D Turker, ... IEEE Journal of Solid-State Circuits 50 (8), 1932-1944, 2015 | 36 | 2015 |
| A wide common-mode fully-adaptive multi-standard 12.5 gb/s backplane transceiver in 28nm cmos J Savoj, K Hsieh, P Upadhyaya, FT An, A Bekele, S Chen, X Jiang, ... 2012 Symposium on VLSI Circuits (VLSIC), 104-105, 2012 | 36 | 2012 |
| A new technique for characterization of digital-to-analog converters in high-speed systems J Savoj, AA Abbasfar, A Amirkhany, BW Garlepp, MA Horowitz 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 31 | 2007 |
| Frequency synthesizer noise reduction MR Ahmadi, J Savoj US Patent 8,604,840, 2013 | 30 | 2013 |
