Another trip to the wall: How much will stacked DRAM benefit HPC? M Radulovic, D Zivanovic, D Ruiz, BR de Supinski, SA McKee, ... Proceedings of the 2015 International Symposium on Memory Systems, 31-36, 2015 | 59 | 2015 |
Main Memory in HPC: Do We Need More or Could We Live with Less? D Zivanovic, M Pavlovic, M Radulovic, H Shin, J Son, SA Mckee, ... ACM Transactions on Architecture and Code Optimization (TACO) 14 (1), 3, 2017 | 53 | 2017 |
Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC K Asifuzzaman, M Pavlovic, M Radulovic, D Zaragoza, O Kwon, KC Ryoo, ... Proceedings of the Second International Symposium on Memory Systems, 40-49, 2016 | 18 | 2016 |
Main memory latency simulation: the missing link RS Verdejo, K Asifuzzaman, M Radulovic, P Radojković, E Ayguadé, ... Proceedings of the International Symposium on Memory Systems, 107-116, 2018 | 17 | 2018 |
PROFET: Modeling System Performance and Energy Without Simulating the CPU M Radulovic, R Sánchez Verdejo, P Carpenter, P Radojković, B Jacob, ... Proceedings of the ACM on Measurement and Analysis of Computing Systems 3 (2 …, 2019 | 10 | 2019 |
Multilevel simulation-based co-design of next generation HPC microprocessors L Zaourar, M Benazouz, A Mouhagir, F Jebali, T Sassolas, JC Weill, ... 2021 International Workshop on Performance Modeling, Benchmarking and …, 2021 | 9 | 2021 |
Large-Memory Nodes for Energy Efficient High-Performance Computing D Zivanovic, M Radulovic, G Llort, D Zaragoza, J Strassburg, ... Proceedings of the Second International Symposium on Memory Systems, 3-9, 2016 | 8 | 2016 |
HPC benchmarking: scaling right and looking beyond the average M Radulovic, K Asifuzzaman, P Carpenter, P Radojković, E Ayguadé Euro-Par 2018: Parallel Processing: 24th International Conference on …, 2018 | 7 | 2018 |
Limpio-LIghtweight MPI instrumentatiOn M Pavlovic, M Radulovic, A Ramirez, P Radojkovic 2015 IEEE 23rd International Conference on Program Comprehension, 303-306, 2015 | 7 | 2015 |
Memory bandwidth and latency in HPC: system requirements and performance impact M Radulović Universitat Politècnica de Catalunya, 2019 | 4 | 2019 |
Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned M Radulovic, K Asifuzzaman, D Zivanovic, N Rajovic, GC de Verdiére, ... 2018 30th International Symposium on Computer Architecture and High …, 2018 | 4 | 2018 |
Industrial single board computer based on OMAP5 processor M Radulovic, M Pavlovic, N Nenadic, G Dimic 2013 2nd Mediterranean Conference on Embedded Computing (MECO), 84-87, 2013 | 4 | 2013 |
Laboratory experimental system for examination of acoustic emission generated by partial discharges I Salom, V Čelebić, J Gajica, N Kartalović, M Mijić, V Sekulić, M Radulović Telfor Journal 5 (2), 134-139, 2013 | 3 | 2013 |
Realization of the teleprotection equipment interface for working with PLC equipment using FPGA logic MI Radulovic, VV Čelebić, MM Kabovic, AV Kabovic 2012 20th Telecommunications Forum (TELFOR), 525-528, 2012 | 3 | 2012 |
Teleprotection terminal interface for analogue communications over high voltage power lines implemented on FPGA VV Čelebić, MM Kabović, MI Radulović, AV Kabović Telfor J. 5 (1), 71-76, 2013 | 1 | 2013 |
Laboratory model for partial discharge diagnostics using acoustic emission measurement I Salom, V Čelebić, J Gajica, N Kartalovic, M Mijic, V Sekulic, M Radulovic 2012 20th Telecommunications Forum (TELFOR), 1220-1223, 2012 | 1 | 2012 |
Concept design of a system for partial discharges diagnostics using single board computer M Radulović, I Salom, V Čelebić, J Gajica, M Pavlović, N Nenadić 2013 21st Telecommunications Forum Telfor (TELFOR), 561-564, 2013 | | 2013 |