Quantifying the benefits of monolithic 3D computing systems enabled by TFT and RRAM AM Felfel, K Datta, A Dutt, H Veluri, A Zaky, AVY Thean, MMS Aly 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 43-48, 2020 | 9 | 2020 |
Floating point multiplication mapping on reram based in-memory computing architecture T Vatwani, A Dutt, D Bhattacharjee, A Chattopadhyay 2018 31st International Conference on VLSI Design and 2018 17th …, 2018 | 6 | 2018 |
Fledge: flexible edge platforms enabled by in-memory computing K Datta, A Dutt, A Zaky, U Chand, D Singh, Y Li, JCY Huang, A Thean, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 4 | 2020 |
TSV-aware 3-D IC structural planning with irregular die-size A Dutt, P Roy, H Rahaman 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 713-716, 2016 | 3 | 2016 |
Pearl: Towards optimization of DNN-accelerators via closed-form analytical representation A Dutt, S Nandy, MM Sabry 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 714-719, 2022 | 2 | 2022 |
East-dnn: Expediting architectural simulations using deep neural networks: Work-in-progress A Dutt, G Narasimman, L Jie, VR Chandrasekhar, MM Sabry Proceedings of the International Conference on Hardware/Software Codesign …, 2019 | 2 | 2019 |
Mami: Majority and multi-input logic on memristive crossbar array D Bhattacharjee, A Dutt, A Chattopadhyay 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 435-438, 2018 | 2 | 2018 |
3-D IC: An Overview of Technologies, Design Methodology, and Test Strategies P Roy, A Dutt, H Rahaman Proceedings of International Conference on Frontiers in Computing and …, 2021 | 1 | 2021 |
Modelling, exploration and optimization of hardware accelerators for deep learning applications A Dutt Nanyang Technological University, 2023 | | 2023 |