| 25.2 A 1.2 V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV DU Lee, KW Kim, KW Kim, H Kim, JY Kim, YJ Park, JH Kim, DS Kim, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 256 | 2014 |
| A 1.2 V 8 Gb 8-channel 128 GB/s high-bandwidth memory (HBM) stacked DRAM with effective I/O test circuits DU Lee, KW Kim, KW Kim, KS Lee, SJ Byeon, JH Kim, JH Cho, J Lee, ... IEEE Journal of Solid-State Circuits 50 (1), 191-203, 2014 | 94 | 2014 |
| Apparatus for pipe latch control circuit in synchronous memory device KW Kim US Patent 6,724,684, 2004 | 87 | 2004 |
| A low cost high performance register-controlled digital DLL for 1 Gbps/spl times/32 DDR SDRAM JT Kwak, CK Kwon, KW Kim, SH Lee, JS Kih 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2003 | 72 | 2003 |
| A 0.1-to-1.5 GHz 4.2 mW all-digital DLL with dual duty-cycle correction circuit and update gear circuit for DRAM in 66nm CMOS technology WJ Yun, HW Lee, D Shin, SD Kang, JY Yang, HO Lee, DU Lee, S Sim, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 41 | 2008 |
| A 1.6 V 1.4 Gbp/s/pin consumer DRAM with self-dynamic voltage scaling technique in 44 nm CMOS technology HW Lee, KH Kim, YK Choi, JH Sohn, NK Park, KW Kim, C Kim, YJ Choi, ... IEEE journal of solid-state circuits 47 (1), 131-140, 2011 | 35 | 2011 |
| A 2.5 Gb/s/pin 256Mb GDDR3 SDRAM with series pipelined CAS latency control and dual-loop digital DLL DU Lee, HW Lee, KC Kwean, YK Choi, HU Moon, SW Kwack, SD Kang, ... 2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006 | 35 | 2006 |
| Multilevel sensing circuit and method thereof KW Kim US Patent 6,137,739, 2000 | 29 | 2000 |
| Synchronous memory device with reduced address pins KW Kim US Patent 6,717,884, 2004 | 27 | 2004 |
| Apparatus for generating data strobe signal applicable to double data rate SDRAM KW Kim US Patent 6,288,971, 2001 | 24 | 2001 |
| DDR SDRAM for stable read operation YJ Yoon, KW Kim US Patent 6,657,908, 2003 | 19* | 2003 |
| Data strobe signal generator of semiconductor device using toggled pull-up and pull-down signals KW Kim US Patent 6,198,674, 2001 | 19 | 2001 |
| An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory (HBM) stacked DRAM DU Lee, KW Kim, KW Kim, KS Lee, SJ Byeon, JH Cho, HH Jin, SK Nam, ... 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 17 | 2014 |
| Data transfer apparatus in semiconductor memory device and method of controlling the same SW Kwack, KW Kim US Patent 7,443,738, 2008 | 17 | 2008 |
| A 7ps-jitter 0.053 mm2 fast-lock addll with wide-range and high-resolution all-digital dcc D Shin, J Song, H Chae, KW Kim, YJ Choi, C Kim 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 17 | 2007 |
| Integrated circuit and method for controlling data output impedance JB Koo, KW Kim US Patent 8,237,464, 2012 | 16 | 2012 |
| Internal voltage generator for semiconductor device KW Kim US Patent 7,227,403, 2007 | 16 | 2007 |
| Multi-slew-rate output driver and optimized impedance-calibration circuit for 66nm 3.0 Gb/s/pin DRAM interface DU Lee, SD Kang, NK Park, HW Lee, YK Choi, JW Lee, SW Kwack, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 14 | 2008 |
| Semiconductor memory device for testifying over-driving quantity depending on position SW Kwack, KW Kim US Patent 7,038,957, 2006 | 14 | 2006 |
| A single-loop DLL using an OR-AND duty-cycle correction technique KS Song, CH Koo, NK Park, KW Kim, YJ Choi, JH Ahn, BT Chung 2008 IEEE Asian Solid-State Circuits Conference, 245-248, 2008 | 12 | 2008 |
