| Analyzing volume diagnosis results with statistical learning for yield improvement H Tang, S Manish, J Rajski, M Keim, B Benware 12th IEEE European Test Symposium (ETS'07), 145-150, 2007 | 108 | 2007 |
| On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. H Tang, SM Reddy, I Pomeranz ITC 3, 1079-1088, 2003 | 102 | 2003 |
| Determining and analyzing integrated circuit yield and quality J Rajski, G Chen, M Keim, N Tamarapalli, M Sharma, H Tang US Patent 7,512,508, 2009 | 95 | 2009 |
| A rapid yield learning flow based on production integrated layout-aware diagnosis M Keim, N Tamarapalli, H Tang, M Sharma, J Rajski, C Schuermyer, ... 2006 IEEE International Test Conference, 1-10, 2006 | 95 | 2006 |
| Integrated circuit yield and quality analysis methods and systems J Rajski, G Chen, M Keim, N Tamarapalli, M Sharma, H Tang US Patent App. 11/221,373, 2006 | 74 | 2006 |
| On testing of interconnect open defects in combinational logic circuits with stems of large fanout SM Reddy, I Pomeranz, H Tang, S Kajihara, K Kinoshita Proceedings. International Test Conference, 83-89, 2002 | 59 | 2002 |
| On efficient X-handling using a selective compaction scheme to achieve high test response compaction ratios H Tang, C Wang, J Rajski, SM Reddy, J Tyszer, I Pomeranz 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 57 | 2005 |
| Defect aware test patterns H Tang, G Chen, SM Reddy, C Wang, J Rajski, I Pomeranz DATE 1, 450-455, 2005 | 55 | 2005 |
| Fault dictionaries for integrated circuit yield and quality analysis methods and systems J Rajski, G Chen, M Keim, N Tamarapalli, M Sharma, H Tang US Patent 7,987,442, 2011 | 53 | 2011 |
| Efficiently performing yield enhancements by identifying dominant physical root cause from test fail data M Sharma, B Benware, L Ling, D Abercrombie, L Lee, M Keim, H Tang, ... 2008 IEEE International Test Conference, 1-9, 2008 | 51 | 2008 |
| Cell-aware diagnosis: Defective inmates exposed in their cells P Maxwell, F Hapke, H Tang 2016 21th IEEE European Test Symposium (ETS), 1-6, 2016 | 42 | 2016 |
| Improved volume diagnosis throughput using dynamic design partitioning X Fan, H Tang, Y Huang, WT Cheng, SM Reddy, B Benware 2012 IEEE International Test Conference, 1-10, 2012 | 40 | 2012 |
| Determining and analyzing integrated circuit yield and quality J Rajski, G Chen, M Keim, N Tamarapalli, M Sharma, H Tang US Patent App. 12/415,806, 2009 | 39 | 2009 |
| Diagnosing cell internal defects using analog simulation-based fault models H Tang, B Benware, M Reese, J Caroselli, T Herrmann, F Hapke, R Tao, ... 2014 IEEE 23rd Asian Test Symposium, 318-323, 2014 | 31 | 2014 |
| Scan chain diagnosis based on unsupervised machine learning Y Huang, B Benware, R Klingenberg, H Tang, J Dsouza, WT Cheng 2017 IEEE 26th Asian Test Symposium (ATS), 225-230, 2017 | 29 | 2017 |
| Interconnect open defect diagnosis with minimal physical information C Liu, W Zou, SM Reddy, WT Cheng, M Sharma, H Tang 2007 IEEE International Test Conference, 1-10, 2007 | 29 | 2007 |
| Generating test patterns having enhanced coverage of untargeted defects J Rajski, H Tang, C Wang US Patent 7,509,600, 2009 | 27 | 2009 |
| On methods to improve location based logic diagnosis W Zou, WT Cheng, SM Reddy, H Tang 19th International Conference on VLSI Design held jointly with 5th …, 2006 | 24 | 2006 |
| Speeding up effect-cause defect diagnosis using a small dictionary W Zou, WT Cheng, SM Reddy, H Tang 25th IEEE VLSI Test Symposium (VTS'07), 225-230, 2007 | 19 | 2007 |
| Diagnose failures caused by multiple locations at a time J Ye, Y Hu, X Li, WT Cheng, Y Huang, H Tang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (4), 824-837, 2013 | 18 | 2013 |
Wu-Tung Chengchief scientist, mentor graphics在 mentor.com 的电子邮件经过验证
