| Radical oxidation of germanium for interface gate dielectric GeO2 formation in metal-insulator-semiconductor gate stack M Kobayashi, G Thareja, M Ishibashi, Y Sun, P Griffin, J McVittie, ... Journal of Applied Physics 106 (10), 2009 | 99 | 2009 |
| Self-aligned 3-D epitaxial structures for MOS device fabrication GA Glass, DB Aubertine, AS Murthy, G Thareja, T Ghani US Patent 9,728,464, 2017 | 98 | 2017 |
| Metal gate-HfO/sub 2/MOS structures on GaAs substrate with and without Si interlayer IJ Ok, H Kim, M Zhang, CY Kang, SJ Rhee, C Choi, SA Krishnan, T Lee, ... IEEE electron device letters 27 (3), 145-147, 2006 | 98 | 2006 |
| High-Performance Gate-All-Around GeOI p-MOSFETs Fabricated by Rapid Melt Growth Using Plasma Nitridation and ALD Gate Dielectric and Self-Aligned … J Feng, G Thareja, M Kobayashi, S Chen, A Poon, Y Bai, PB Griffin, ... IEEE Electron Device Letters 29 (7), 805-807, 2008 | 82 | 2008 |
| Ultrathin HfO2 (equivalent oxide thickness= 1.1 nm) metal-oxide-semiconductor capacitors on n-GaAs substrate with germanium passivation HS Kim, I Ok, M Zhang, C Choi, T Lee, F Zhu, G Thareja, L Yu, JC Lee Applied physics letters 88 (25), 2006 | 72 | 2006 |
| Doped polar layers and semiconductor device incorporating same R Ramamoorthy, S Manipatruni, G Thareja US Patent 11,164,976, 2021 | 69 | 2021 |
| Conversion of thin transistor elements from silicon to silicon germanium GA Glass, DB Aubertine, AS Murthy, G Thareja, SM Cea US Patent 8,957,476, 2015 | 57 | 2015 |
| High n-Type Antimony Dopant Activation in Germanium Using Laser Annealing for Junction Diode G Thareja, S Chopra, B Adams, Y Kim, S Moffatt, K Saraswat, Y Nishi IEEE electron device letters 32 (7), 838-840, 2011 | 53 | 2011 |
| Doped polar layers and semiconductor device incorporating same R Ramamoorthy, S Manipatruni, G Thareja US Patent 11,398,570, 2022 | 52 | 2022 |
| Integration method of ferroelectric memory array G Thareja, S Manipatruni, RK Dokania, R Ramesh, A Mathuriya US Patent 11,289,497, 2022 | 52 | 2022 |
| High performance germanium n-MOSFET with antimony dopant activation beyond 1×1020cm−3 G Thareja, J Liang, S Chopra, B Adams, N Patil, SL Cheng, A Nainani, ... 2010 International Electron Devices Meeting, 10.5. 1-10.5. 4, 2010 | 48 | 2010 |
| Electrical Characteristics of GermaniumJunctions Obtained Using Rapid Thermal Annealing of Coimplanted P and Sb G Thareja, SL Cheng, T Kamins, K Saraswat, Y Nishi IEEE electron device letters 32 (5), 608-610, 2011 | 46 | 2011 |
| Ferroelectric capacitor and method of patterning such G Thareja, S Manipatruni, RK Dokania, R Ramesh, A Mathuriya US Patent 11,430,861, 2022 | 43 | 2022 |
| Doped polar layers and semiconductor device incorporating same R Ramamoorthy, S Manipatruni, G Thareja US Patent 11,469,327, 2022 | 41 | 2022 |
| Doped polar layers and semiconductor device incorporating same R Ramamoorthy, S Manipatruni, G Thareja US Patent 11,444,203, 2022 | 41 | 2022 |
| Low power ferroelectric based majority logic gate adder S Manipatruni, YS Fang, R Menezes, RK Dokania, G Thareja, R Ramesh, ... US Patent 10,944,404, 2021 | 37 | 2021 |
| Low power ferroelectric based majority logic gate carry propagate and serial adder S Manipatruni, YS Fang, R Menezes, RK Dokania, G Thareja, R Ramesh, ... US Patent 11,283,453, 2022 | 36 | 2022 |
| Ferroelectric capacitor integrated with logic G Thareja, S Manipatruni, RK Dokania, R Ramesh, A Mathuriya US Patent 11,522,044, 2022 | 33 | 2022 |
| Structural advantage for the EOT scaling and improved electron channel mobility by incorporating dysprosium oxide (Dy/sub 2/O/sub 3/) into HfO/sub 2/n-MOSFETs T Lee, SJ Rhee, CY Kang, F Zhu, H Kim, C Choi, I Ok, M Zhang, ... IEEE electron device letters 27 (8), 640-643, 2006 | 33 | 2006 |
| Method for using and forming low power ferroelectric based majority logic gate adder S Manipatruni, YS Fang, R Menezes, RK Dokania, G Thareja, R Ramesh, ... US Patent 11,502,691, 2022 | 32 | 2022 |
