| A 9-bit 80 MS/s successive approximation register analog-to-digital converter with a capacitor reduction technique YK Cho, YD Jeon, JW Nam, JK Kwon IEEE Transactions on Circuits and Systems II: Express Briefs 57 (7), 502-506, 2010 | 74 | 2010 |
| A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS YD Jeon, YK Cho, JW Nam, KD Kim, WY Lee, KT Hong, JK Kwon IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 65 | 2010 |
| Multiple-gate MOS transistor and a method of manufacturing the same Y Cho, S Kwon, T Roh, D Lee, J Kim US Patent App. 10/989,006, 2005 | 53 | 2005 |
| Dual structure FinFET and method of manufacturing the same YK Cho, TM Roh, JD Kim US Patent 7,759,737, 2010 | 35 | 2010 |
| A low switching noise and high-efficiency buck converter using a continuous-time reconfigurable delta-sigma modulator YK Cho, MD Kim, CY Kim IEEE Transactions on Power Electronics 33 (12), 10501-10511, 2018 | 26 | 2018 |
| Multi-stage dual successive approximation register analog-to-digital convertor and method of performing analog-to-digital conversion using the same YD Jeon, YK Cho, JW Nam, JK Kwon US Patent 7,978,117, 2011 | 26 | 2011 |
| Noninverting buck–boost DC–DC converter using a duobinary-encoded single-bit delta-sigma modulator YK Cho, KC Lee IEEE Transactions on Power Electronics 35 (1), 484-495, 2019 | 25 | 2019 |
| A frequency reconfigurable dipole antenna with solid-state plasma in silicon DJ Kim, ES Jo, YK Cho, J Hur, CK Kim, CH Kim, B Park, D Kim, YK Choi Scientific reports 8 (1), 14996, 2018 | 24 | 2018 |
| A 9-bit 100-MS/s Flash-SAR ADC without Track-and-Hold Circuits YK Cho, JH Jung, KC Lee 2012 International Symposium on Wireless Communication Systems (ISWCS), 880-884, 2012 | 21 | 2012 |
| Successive approximation register analog-digital converter and method for operating the same YK Cho, YD Jeon, JW Nam, JK Kwon US Patent 8,164,504, 2012 | 21 | 2012 |
| Digital-to-analog converter YK Cho, YD Jeon, JW Nam, JK Kwon US Patent 8,059,022, 2011 | 19 | 2011 |
| Band-gap reference voltage generator YK Cho, YD Jeon, JW Nam, JK Kwon US Patent 8,058,863, 2011 | 17 | 2011 |
| Operational amplifier YK Cho US Patent 5,894,245, 1999 | 17 | 1999 |
| Apparatus and method for calibrating offset voltage and continuous time delta-sigma modulation apparatus including the same YK Cho, JH Jung, K Lee US Patent 8,791,846, 2014 | 16 | 2014 |
| High‐gain sub‐terahertz lens horn antenna with a metal guide JN Lee, YK Cho, JH Jung, SB Hyun Electronics Letters 56 (14), 689-691, 2020 | 15 | 2020 |
| A low-power continuous-time delta-sigma modulator using a resonant single op-amp third-order loop filter YK Cho, MD Kim, CY Kim IEEE Transactions on Circuits and Systems II: Express Briefs 65 (7), 854-858, 2017 | 14 | 2017 |
| Successive approximation register analog-digital converter and method of driving the same YK Cho, YD Jeon, JW Nam, JK Kwon US Patent 7,893,860, 2011 | 14 | 2011 |
| Single op‐amp second‐order loop filter for continuous‐time delta–sigma modulators YK Cho, BH Park Electronics Letters 51 (8), 619-621, 2015 | 13 | 2015 |
| Analog-digital converter and power saving method thereof J Nam, YK Cho, YS Yamg US Patent 8,692,702, 2014 | 13 | 2014 |
| Multiple-gate MOS transistor using Si substrate and method of manufacturing the same YK Cho, TM Roh, JD Kim US Patent 7,605,039, 2009 | 13 | 2009 |
Choul-Young KimChungnam National University在 cnu.ac.kr 的电子邮件经过验证
Choul-Young KimChungnam National University在 cnu.ac.kr 的电子邮件经过验证
Seunghyun JangETRI在 etri.re.kr 的电子邮件经过验证
Jung Nam LeeElectronics and Telecommunications Research Institute在 etri.re.kr 的电子邮件经过验证