| A 9-bit 80 MS/s successive approximation register analog-to-digital converter with a capacitor reduction technique YK Cho, YD Jeon, JW Nam, JK Kwon IEEE Transactions on Circuits and Systems II: Express Briefs 57 (7), 502-506, 2010 | 76 | 2010 |
| A 12-bit 1.6, 3.2, and 6.4 GS/s 4-b/cycle time-interleaved SAR ADC with dual reference shifting and interpolation JW Nam, M Hassanpourghadi, A Zhang, MSW Chen IEEE Journal of Solid-State Circuits 53 (6), 1765-1779, 2018 | 73 | 2018 |
| A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS YD Jeon, YK Cho, JW Nam, KD Kim, WY Lee, KT Hong, JK Kwon IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 65 | 2010 |
| Multi-stage dual successive approximation register analog-to-digital convertor and method of performing analog-to-digital conversion using the same YD Jeon, YK Cho, JW Nam, JK Kwon US Patent 7,978,117, 2011 | 26 | 2011 |
| An embedded passive gain technique for asynchronous SAR ADC achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS JW Nam, MSW Chen IEEE Transactions on Circuits and Systems I: Regular Papers 63 (10), 1628-1638, 2016 | 22 | 2016 |
| A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS JW Nam, M Hassanpourghadi, A Zhang, MSW Chen 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016 | 21 | 2016 |
| A dual-channel pipelined ADC with sub-ADC based on Flash–SAR architecture YD Jeon, JW Nam, KD Kim, TM Roh, JK Kwon IEEE Transactions on Circuits and Systems II: Express Briefs 59 (11), 741-745, 2012 | 21 | 2012 |
| Successive approximation register analog-digital converter and method for operating the same YK Cho, YD Jeon, JW Nam, JK Kwon US Patent 8,164,504, 2012 | 21 | 2012 |
| Digital-to-analog converter YK Cho, YD Jeon, JW Nam, JK Kwon US Patent 8,059,022, 2011 | 19 | 2011 |
| Band-gap reference voltage generator YK Cho, YD Jeon, JW Nam, JK Kwon US Patent 8,058,863, 2011 | 17 | 2011 |
| Compact SRAM-based PUF chip employing body voltage control technique JW Nam, JH Ahn, JP Hong IEEE Access 10, 22311-22319, 2022 | 14 | 2022 |
| Successive approximation register analog-digital converter and method of driving the same YK Cho, YD Jeon, JW Nam, JK Kwon US Patent 7,893,860, 2011 | 14 | 2011 |
| Analog-digital converter and power saving method thereof J Nam, YK Cho, YS Yamg US Patent 8,692,702, 2014 | 13 | 2014 |
| A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS JW Nam, D Chiong, MSW Chen Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013 | 11 | 2013 |
| Offset-voltage calibration circuit YK Cho, YD Jeon, JW Nam, JK Kwon US Patent 8,264,268, 2012 | 11 | 2012 |
| Multi-stage successive approximation register analog-to-digital converter and analog-to-digital converting method using the same YD Jeon, YK Cho, JW Nam, JK Kwon US Patent 7,999,719, 2011 | 11 | 2011 |
| Motor control device and method of controlling the same J Nam, YK Cho, HD Lee, YS Yang, JK Kwon, J Kim US Patent 9,490,734, 2016 | 10 | 2016 |
| High-speed multi-stage voltage comparator YK Cho, YD Jeon, JW Nam, JK Kwon US Patent 7,977,979, 2011 | 9 | 2011 |
| A low-power class-C voltage-controlled oscillator with robust start-up and compact high-Q capacitor array YK Cho, JW Nam, SW Lee IEEE Transactions on Circuits and Systems II: Express Briefs 69 (3), 819-823, 2021 | 8 | 2021 |
| Machine-learning based analog and mixed-signal circuit design and optimization JW Nam, YK Lee 2021 International Conference on Information Networking (ICOIN), 874-876, 2021 | 8 | 2021 |
