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Oreste Madia
Oreste Madia
在 tsmc.com 的电子邮件经过验证
标题
引用次数
引用次数
年份
Method for forming a semiconductor device structure comprising a gate fill metal
Q Xie, C Zhu, K Shrestha, P Calka, O Madia, JW Maes, ME Givens
US Patent 10,607,895, 2020
3412020
Method for forming a semiconductor device structure and related semiconductor device structures
Q Xie, C Zhu, K Shrestha, P Calka, O Madia, JW Maes, ME Givens
US Patent App. 16/834,657, 2020
2492020
Selective PEALD of oxide on dielectric
E Tois, V Pore, S Haukka, T Suzuki, L Jia, SJ Kim, O Madia
US Patent 11,170,993, 2021
2072021
Ultra-low-k cyclic carbon-bridged PMO films with a high chemical resistance
F Goethals, I Ciofi, O Madia, K Vanstreels, MR Baklanov, C Detavernier, ...
Journal of Materials Chemistry 22 (17), 8281-8286, 2012
572012
Intrinsic electron traps in atomic-layer deposited HfO2 insulators
F Cerbu, O Madia, DV Andreev, S Fadida, M Eizenberg, L Breuil, ...
Applied Physics Letters 108 (22), 2016
542016
Density and Capture Cross-Section of Interface Traps in GeSnO2 and GeO2 Grown on Heteroepitaxial GeSn
S Gupta, E Simoen, R Loo, O Madia, D Lin, C Merckling, Y Shimura, ...
ACS applied materials & interfaces 8 (21), 13181-13186, 2016
292016
Spectroscopy of deep gap states in high-k insulators
VV Afanas' ev, WC Wang, F Cerbu, O Madia, M Houssa, A Stesmans
ECS Transactions 64 (8), 17, 2014
212014
Plasma enhanced deposition processes for controlled formation of oxygen containing thin films
L Jia, VJ Pore, M Tuominen, SJ Kim, O Madia
US Patent 11,158,500, 2021
142021
Improved Methodology for Integrated -Value Extractions
I Ciofi, G Borrello, O Madia, CJ Wilson, B Vereecke, GP Beyer
IEEE transactions on electron devices 59 (6), 1607-1613, 2012
72012
Impact of strain on the passivation efficiency of Ge dangling bond interface defects in condensation grown SiO2/GexSi1− x/SiO2/(1 0 0) Si structures with nm-thin GexSi1− x layers
O Madia, APD Nguyen, NH Thoan, V Afanas’ev, A Stesmans, L Souriau, ...
Applied surface science 291, 11-15, 2014
52014
Saturation Photo-Voltage Methodology for Semiconductor/Insulator Interface Trap Spectroscopy
O Madia, VV Afanas' ev, D Cott, H Arimura, C Schulte-Braucks, HC Lin, ...
ECS Journal of Solid State Science and Technology 5 (4), P3031, 2015
32015
Experimental characterization of BTI defects
B Kaczer, VV Afanas' ev, K Rott, F Cerbu, J Franco, W Goes, T Grasser, ...
2013 International Conference on Simulation of Semiconductor Processes and …, 2013
32013
Atomic layer deposition of indium gallium zinc oxide
O Madia, A Illiberi, ME Givens, T Ivanova, C Dezelah, V Sharma
US Patent 11,664,222, 2023
22023
Selective deposition of SiOC thin films
JW Maes, DK De Roest, O Madia
US Patent 11,139,163, 2021
22021
Selective deposition of SiOC thin films
JW Maes, DK De Roest, O Madia
US Patent 11,664,219, 2023
12023
Germanium-related deep electron traps in ALD-grown HfO2 insulators studied through Exhaustive PhotoDepopulation Spectroscopy
O Madia, VV Afanas’ev, JA Kittl, WK Hong, SS Kim, HY Lee, S Kim, ...
Microelectronic Engineering 147, 188-191, 2015
12015
Charge transition level of GePb1 centers at interfaces of SiO2/GexSi1−x/SiO2 heterostructures investigated by positron annihilation spectroscopy
O Madia, N Segercrantz, V Afanas' ev, A Stesmans, L Souriau, J Slotte, ...
physica status solidi (b) 251 (11), 2211-2215, 2014
12014
Semiconductor device and fabrication method thereof
O Madia, G Vellianitis, G Doornbos, MJH Van Dal
US Patent 12,002,860, 2024
2024
Method for forming a semiconductor device structure and related semiconductor device structures
Q Xie, C Zhu, K Shrestha, P Calka, O Madia, JW Maes, ME Givens
US Patent App. 18/522,867, 2024
2024
Memory device and method of fabricating the same
MJH Van Dal, G Vellianitis, G Doornbos, O Madia
US Patent App. 18/152,160, 2024
2024
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