| Accelerating apache spark with fpgas E Ghasemi, P Chow Concurrency and Computation: Practice and Experience 31 (2), e4222, 2019 | 26 | 2019 |
| Accelerating apache spark big data analysis with fpgas E Ghasemi, P Chow 2016 Intl IEEE Conferences on Ubiquitous Intelligence & Computing, Advanced …, 2016 | 23 | 2016 |
| Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructions A Ng, E Delaye, E Ghasemi, X Teng, J Zejda, Y Wu, S Settle, A Sirasao US Patent 11,620,490, 2023 | 10 | 2023 |
| Neural network pruning and hardware acceleration T Jeong, E Ghasemi, J Tuyls, E Delaye, A Sirasao 2020 IEEE/ACM 13th International Conference on Utility and Cloud Computing …, 2020 | 8 | 2020 |
| Circuit arrangements and methods for performing multiply-and-accumulate operations E Ghasemi, E Delaye, A Sirasao, S Settle US Patent 10,572,225, 2020 | 8 | 2020 |
| Circuit arrangements and methods for dividing a three-dimensional input feature map E Ghasemi, E Delaye, A Sirasao US Patent 10,411,709, 2019 | 8 | 2019 |
| A scalable heterogeneous dataflow architecture for big data analytics using fpgas E Ghasemi University of Toronto (Canada), 2015 | 8 | 2015 |
| Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit A Sirasao, E Delaye, A Ng, E Ghasemi US Patent 10,460,416, 2019 | 7 | 2019 |
| Software-driven design optimization for fixed-point multiply-accumulate circuitry A Sirasao, E Delaye, S Settle, Z Ma, E Ghasemi, X Teng, A Ng, J Zejda US Patent 10,943,039, 2021 | 5 | 2021 |
| Software-driven design optimization for mapping between floating-point and fixed-point multiply accumulators S Settle, E Delaye, A Ng, E Ghasemi, A Sirasao, X Teng, J Zejda US Patent 10,678,509, 2020 | 4 | 2020 |
| Circuit arrangements and methods for traversing input feature maps E Ghasemi, E Delaye, A Sirasao US Patent 11,106,968, 2021 | 3 | 2021 |
| Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit A Sirasao, E Delaye, A Ng, E Ghasemi US Patent 10,984,500, 2021 | 1 | 2021 |
| Dynamically structured single instruction, multiple data (SIMD) instructions S Settle, E Ghasemi, A Sirasao, RD Wittig US Patent 10,824,434, 2020 | 1 | 2020 |
| Exploration and Tradeoffs of different Kernels in FPGA Deep Learning Applications E Delaye, A Sirasao, E Ghasemi Proceedings of the 2018 International Symposium on Physical Design, 42-47, 2018 | 1 | 2018 |
| Instruction generation and programming model for a data processing array and microcontroller J Tuyls, X Teng, S Pandit, R Patwari, Q Zhou, E Ghasemi, EC Wu, ... US Patent App. 17/823,902, 2024 | | 2024 |
| Instruction set architecture for data processing array control X Teng, T Siddagangaiah, B Lozano, E Ghasemi, R Patwari, E Delaye, ... US Patent App. 17/818,309, 2024 | | 2024 |
| Reconfigurable neural engine with extensible instruction set architecture S Pandit, J Tuyls, X Teng, R Patwari, E Ghasemi, E Delaye, A Ng US Patent App. 17/814,817, 2024 | | 2024 |
| Hardware acceleration of machine learning designs E Ghasemi, R Patwari, E Delaye, J Tuyls, EC Wu, X Teng, S Pandit US Patent App. 17/806,906, 2023 | | 2023 |
| Machine learning runtime library for neural network acceleration A Ng, J Zejda, E Delaye, X Teng, S Santan, ST Soe, A Sirasao, ... US Patent 11,694,066, 2023 | | 2023 |
| NEURONAL MULTICOUCHE NETWORK PROCESSING BY A NEURONAL NETWORK ACCELERATOR USING CONTAINED HOST COMMUNICATION WEIGHTS AND A LAYERED INSTRUCTION PACKAGE A Ng, E Delaye, E Ghasemi, T Xiao, J Zejda, Y Wu, S Settle, A Sirasao | | 2019 |
