| In-datacenter performance analysis of a tensor processing unit NP Jouppi, C Young, N Patil, D Patterson, G Agrawal, R Bajwa, S Bates, ... Proceedings of the 44th annual international symposium on computer …, 2017 | 5750 | 2017 |
| Tpu v4: An optically reconfigurable supercomputer for machine learning with hardware support for embeddings N Jouppi, G Kurian, S Li, P Ma, R Nagarajan, L Nai, N Patil, ... Proceedings of the 50th Annual International Symposium on Computer …, 2023 | 262 | 2023 |
| Matrix processing apparatus R Narayanaswami, R Nagarajan, DH Woo, CD Leary US Patent 9,798,701, 2017 | 9 | 2017 |
| Matrix processing apparatus R Narayanaswami, R Nagarajan, DH Woo, CD Leary US Patent 9,805,001, 2017 | 7 | 2017 |
| Load balancing for memory channel controllers R Nagarajan, H Hariharan US Patent 11,222,258, 2022 | 5 | 2022 |
| Matrix processing apparatus R Narayanaswami, R Nagarajan, DH Woo, CD Leary US Patent 9,898,441, 2018 | 5 | 2018 |
| Matrix processing apparatus R Narayanaswami, R Nagarajan, DH Woo, CD Leary US Patent 9,880,976, 2018 | 5 | 2018 |
| Matrix processing apparatus R Narayanaswami, R Nagarajan, DH Woo, CD Leary US Patent 10,417,303, 2019 | 4 | 2019 |
| Matrix processing apparatus R Narayanaswami, R Nagarajan, DH Woo, CD Leary US Patent 10,719,575, 2020 | 3 | 2020 |
| Accelerated embedding layer computations R Nagarajan, L Nai, G Kurian, H Hariharan US Patent 11,651,209, 2023 | 2 | 2023 |
| Structures on intuitionistic Q-fuzzy quotient sublattices in terms of fuzzy lattice S Subramanian, R Nagarajan, B Chellapa Internal Rev. Fuzzy Math. 6 (1), 33-43, 2011 | 2 | 2011 |
| On-chip interconnect for memory channel controllers R Nagarajan, H Hariharan US Patent 12,007,913, 2024 | 1 | 2024 |
| Load balancing for memory channel controllers R Nagarajan, H Hariharan US Patent App. 17/563,509, 2022 | 1 | 2022 |
| Method to Detect Silent Data Corruption (SDC) for SIMD Compute Units R Nagarajan US Patent App. 18/124,390, 2024 | | 2024 |
| Accelerated embedding layer computations R Nagarajan, L Nai, G Kurian, H Hariharan US Patent App. 18/582,294, 2024 | | 2024 |
| Sparse SIMD Cross-lane Processing Unit R Nagarajan, S Subramanian, AC Jacob US Patent App. 18/597,005, 2024 | | 2024 |
| Streaming Transfers and Ordering Model R Nagarajan, AC Jacob, S Subramanian, H Hariharan US Patent App. 18/596,835, 2024 | | 2024 |
| Cooperative Instruction Prefetch on Multicore System R Nagarajan, C Leary, TM Vijayaraj, TJ Norrie US Patent App. 18/595,866, 2024 | | 2024 |
| Streaming transfers and ordering model R Nagarajan, AC Jacob, S Subramanian, H Hariharan US Patent 11,977,499, 2024 | | 2024 |
| Cooperative instruction prefetch on multicore system R Nagarajan, C Leary, TM Vijayaraj, TJ Norrie US Patent 11,972,263, 2024 | | 2024 |
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