| Time integrator for mixed-mode signal processing YJ Park, D Jarrett-Amor, F Yuan 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 826-829, 2016 | 22 | 2016 |
| A 32 Gb/s, 0.42 pJ/bit Passive Hybrid Simultaneous Bidirectional Transceiver for Die-to-Die Links D Jarrett-Amor, K Yadav, D Zhang, B Yang, S Jalali, TC Carusone 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | 2 | 2023 |
| Time-mode techniques for fast-locking phase-locked loops D Jarrett-Amor, YJ Park, F Yuan 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1790-1793, 2016 | 2 | 2016 |
| Low-power integrating frequency difference-to-voltage converter with applications in injection-locked FLL D Jarrett-Amor, F Yuan Analog Integrated Circuits and Signal Processing 95 (1), 53-65, 2018 | 1 | 2018 |
| Data transient insensitive phase-locked loops D Jarrett-Amor, F Yuan 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 1-4, 2016 | | 2016 |
| Frequency calibration of the system clock of passive wireless microsystems D Jarrett-Amor Toronto Metropolitan University, 0 | | |
Fei YuanRyerson University在 ryerson.ca 的电子邮件经过验证
Fei YuanRyerson University在 ryerson.ca 的电子邮件经过验证