| A high speed binary floating point multiplier using Dadda algorithm B Jeevan, S Narender, CVK Reddy, K Sivani (iMac4s), 2013 International Multi-Conference on, 2013 | 31 | 2013 |
| A new high-speed multiplier based on carry-look-ahead adder and compressor B Jeevan, K Sivani VLSI Design: Circuits, Systems and Applications: Select Proceedings of …, 2018 | 13 | 2018 |
| Simulation and synthesis of UART through FPGA Zedboard for IoT applications B Jeevan, P Sahithi, P Samskruthi, K Sivani 2022 International Conference on Advances in Computing, Communication and …, 2022 | 10 | 2022 |
| FPGA implementation of secure image compression with 2D-DCT using Verilog HDL B Jeevan, CN Bhatt, CV Krishna, K Sivani Devices, Circuits and Systems (ICDCS), 2014 2nd International Conference on, 2014 | 9 | 2014 |
| Design of efficient 22 nm, 20-FinFET full adder for low-power and high-speed arithmetic units J Battini, S Kosaraju Silicon 15 (2), 993-1002, 2023 | 7 | 2023 |
| A 16 nm finfet circuit with triple function as digital multiplexer, active-high and active-low output decoder for high-performance sram architecture B Jeevan, K Sivani Semiconductor Science and Technology 37 (8), 085021, 2022 | 7 | 2022 |
| A Review on different Logic Styles to design High Performance VLSI Decoders B Jeevan, K Sivani 2018 International Conference on Networking, Embedded and Wireless Systems …, 2018 | 7 | 2018 |
| Design of 0.8 V, 22 nm DG-FinFET based efficient VLSI multiplexers B Jeevan, K Sivani Microelectronics Journal 113, 105059, 2021 | 6 | 2021 |
| Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units B Jeevan, K Bikshalu, K Sivani Microprocessors and Microsystems 99, 104846, 2023 | 2 | 2023 |
| A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block B Jeevan, K Bikshalu, K Sivani Engineering Research Express 5 (1), 015077, 2023 | 1 | 2023 |
| Implementation of parallel multiplier based on Booth computing method using FPGA B Jeevan, P Samskruthi, P Sahithi, K Sivani 2022 International Conference on Advances in Computing, Communication and …, 2022 | 1 | 2022 |
| Design of 64-bit Signed Magnitude Comparator using FPGA for IoT applications B Jeevan, K Sivani 2022 International Conference on Advances in Computing, Communication and …, 2022 | 1 | 2022 |
| An efficient single-stage carry select adder using excess-1 FinFET circuit in 22 nm technology J Battini, S Kosaraju Semiconductor Science and Technology 39 (9), 095011, 2024 | | 2024 |
| A new 18nm FinFET-based Programmable Logic Array type Multiplexer for High-speed and Low-Power applications B Jeevan, K Sivani 2023 IEEE 20th India Council International Conference (INDICON), 1205-1210, 2023 | | 2023 |
| A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology J BATTINI, N PASHYA, S KOSARAJU | | 2023 |
| Heterogeneous Logic: a High Performance and Low Power Non-CMOS 4-1 Multiplexer B Jeevan, K Sivani | | |
| Improvement of FinFET based Digital VLSI Decoders Multiplexers and their Applications B JEEVAN Warangal, 0 | | |
kosaraju sivaniprofessor of E&I在 kitsw.ac.in 的电子邮件经过验证
