| A 14 nm FinFET 128 Mb SRAM With VEnhancement Techniques for Low-Power Applications T Song, W Rim, J Jung, G Yang, J Park, S Park, Y Kim, KH Baek, S Baek, ... IEEE Journal of Solid-State Circuits 50 (1), 158-169, 2014 | 186 | 2014 |
| A 10 nm FinFET 128 Mb SRAM with assist adjustment system for power, performance, and area optimization T Song, W Rim, S Park, Y Kim, G Yang, H Kim, S Baek, J Jung, B Kwon, ... IEEE Journal of Solid-State Circuits 52 (1), 240-249, 2016 | 115 | 2016 |
| A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications T Song, J Jung, W Rim, H Kim, Y Kim, C Park, J Do, S Park, S Cho, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 198-200, 2018 | 72 | 2018 |
| Semiconductor integrated circuit, method of designing the same, and method of fabricating the same TJ Song, P Ko, GH Kim, JH Jung US Patent 9,026,975, 2015 | 42 | 2015 |
| Static random access memory devices having read and write assist circuits therein that improve read and write reliability J Jung, S Sim US Patent 8,995,208, 2015 | 37 | 2015 |
| Negative voltage generator and semiconductor memory device TJ Song, GH Kim, JS Choi, SH Sim, I Park, CH Lee, H Choi, JH Jung US Patent 8,934,313, 2015 | 33 | 2015 |
| Semiconductor device including a gate electrode and a conductive structure JH Do, S Lee, J Jung, J Lim, G Yang, B Sanghoon, T Song US Patent 10,541,243, 2020 | 27 | 2020 |
| Static memory device and static random access memory device JH Jung, SH Sim, JM Choi US Patent 8,018,788, 2011 | 27 | 2011 |
| 24.3 A 3nm gate-all-around SRAM featuring an adaptive dual-BL and an adaptive cell-power assist circuit T Song, W Rim, H Kim, KH Cho, T Kim, TJ Lee, G Bae, DW Kim, SD Kwon, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 338-340, 2021 | 26 | 2021 |
| Semiconductor device layout having a power rail JH Jung US Patent 9,865,544, 2018 | 22 | 2018 |
| 12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis T Song, H Kim, W Rim, Y Kim, S Park, C Park, M Hong, G Yang, J Do, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 208-209, 2017 | 18 | 2017 |
| Semiconductor device T Song, DO Jungho, S Lee, J Jung US Patent 10,505,546, 2019 | 17 | 2019 |
| Semiconductor device JH Jung US Patent 9,825,024, 2017 | 15 | 2017 |
| Power gating circuit, system on chip circuit including the same and power gating method DW Seo, JH Jung, I Park, CH Lee US Patent 7,782,701, 2010 | 14 | 2010 |
| Integrated circuits having cross-couple constructs and semiconductor devices including integrated circuits JH Do, LEE Dal-Hee, J Lim, TJ Song, JH Jung US Patent 11,335,673, 2022 | 13 | 2022 |
| Integrated circuit including standard cells overlapping each other and method of generating layout of the integrated circuit JH Do, JH Jung, JS Yu, SY Lee, TJ Song, JB Lee US Patent 10,579,771, 2020 | 13 | 2020 |
| Semiconductor device including a field effect transistor JH Do, W Rim, YU Jisu, J Jung US Patent 10,332,870, 2019 | 12 | 2019 |
| Integrated circuit having vertical transistor and semiconductor device including the integrated circuit JH Do, S Baek, TJ Song, JH Jung, SY Lee US Patent 10,573,643, 2020 | 11 | 2020 |
| Circuit and method of driving a word line by changing the capacitance of a clamp capacitor to compensate for a fluctuation of a power supply voltage level JH Jung, MK Seo, H Lee, HJ Bang US Patent 7,394,701, 2008 | 11 | 2008 |
| A 3-nm gate-all-around SRAM featuring an adaptive dual-Bitline and an adaptive cell-power assist circuit T Song, H Kim, W Rim, H Jung, C Park, I Lee, S Baek, J Jung IEEE Journal of Solid-State Circuits 57 (1), 236-244, 2021 | 10 | 2021 |
