| A reliable 8T SRAM for high-speed searching and logic-in-memory operations J Chen, W Zhao, Y Wang, Y Shu, W Jiang, Y Ha IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (6), 769-780, 2022 | 27 | 2022 |
| Efficient FPGA implementation of K-nearest-neighbor search algorithm for 3D LIDAR localization and mapping in smart vehicles H Sun, X Liu, Q Deng, W Jiang, S Luo, Y Ha IEEE Transactions on Circuits and Systems II: Express Briefs 67 (9), 1644-1648, 2020 | 27 | 2020 |
| A 55nm, 0.4 V 5526-TOPS/W compute-in-memory binarized CNN accelerator for AIoT applications H Zhang, Y Shu, W Jiang, Z Yin, W Zhao, Y Ha IEEE Transactions on Circuits and Systems II: Express Briefs 68 (5), 1695-1699, 2021 | 26 | 2021 |
| A High-Throughput Full-Dataflow MobileNetv2 Accelerator on Edge FPGA J Weixiong, Y Heng, H Yajun IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022 | 14 | 2022 |
| Optimizing energy efficiency of CNN-based object detection with dynamic voltage and frequency scaling W Jiang, H Yu, J Zhang, J Wu, S Luo, Y Ha Journal of Semiconductors 41 (2), 022406, 2020 | 14 | 2020 |
| Wsq-addernet: Efficient weight standardization based quantized addernet fpga accelerator design with high-density int8 dsp-lut co-packing optimization Y Zhang, B Sun, W Jiang, Y Ha, M Hu, W Zhao Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022 | 12 | 2022 |
| Tait: One-shot full-integer lightweight dnn quantization via tunable activation imbalance transfer W Jiang, H Yu, X Liu, H Sun, R Li, Y Ha 2021 58th ACM/IEEE Design Automation Conference (DAC), 1027-1032, 2021 | 11 | 2021 |
| DVFS-based scrubbing scheduling for reliability maximization on parallel tasks in SRAM-based FPGAs R Li, H Yu, W Jiang, Y Ha 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 10 | 2020 |
| Quality optimization of adaptive applications via deep reinforcement learning in energy harvesting edge devices F Chen, H Yu, W Jiang, Y Ha IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 9 | 2022 |
| Energy efficiency optimization of FPGA-based CNN accelerators with full data reuse and VFS W Jiang, H Yu, X Liu, Y Ha 2019 26th IEEE International Conference on Electronics, Circuits and Systems …, 2019 | 7 | 2019 |
| AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA W Jiang, H Yu, F Chen, Y Ha IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2023 | 6 | 2023 |
| FODM: A framework for accurate online delay measurement supporting all timing paths in FPGA W Jiang, H Yu, H Zhang, Y Shu, R Li, J Chen, Y Ha IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (4), 502-514, 2022 | 5 | 2022 |
| An accurate FPGA online delay monitor supporting all timing paths W Jiang, R Li, H Yu, Y Ha 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 4 | 2020 |
| Enabling fine-grained dynamic voltage and frequency scaling in SDSoC W Jiang, H Yu, Y Ha 2019 32nd IEEE International System-on-Chip Conference (SOCC), 56-61, 2019 | 4 | 2019 |
| FiDRL: Flexible Invocation-Based Deep Reinforcement Learning for DVFS Scheduling in Embedded Systems J Li, W Jiang, Y He, Q Yang, A Gao, Y Ha, E Özcan, R Bai, T Cui, H Yu IEEE Transactions on Computers, 2024 | | 2024 |
| RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy R Li, L Li, H Yu, M Fujita, W Jiang, Y Ha IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | | 2024 |
| Automatic overclocking controller based on circuit delay measurement W Jiang, Y Ha US Patent App. 18/224,579, 2024 | | 2024 |
| A Deep Investigation on Stealthy DVFS Fault Injection Attacks at DNN Hardware Accelerators J Xu, F Zhang, W Jin, K Yang, Z Wang, W Jiang, Y Ha IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | | 2024 |
| Pure integer quantization method for lightweight neural network (LNN) W Jiang, Y Ha US Patent 11,934,954, 2024 | | 2024 |
| Full-path circuit delay measurement device for field-programmable gate array (FPGA) and measurement method W Jiang, Y Ha US Patent 11,762,015, 2023 | | 2023 |
