| P4: Programming protocol-independent packet processors P Bosshart, D Daly, G Gibb, M Izzard, N McKeown, J Rexford, ... ACM SIGCOMM Computer Communication Review 44 (3), 87-95, 2014 | 3587 | 2014 |
| Forwarding metamorphosis: Fast programmable match-action processing in hardware for SDN P Bosshart, G Gibb, HS Kim, G Varghese, N McKeown, M Izzard, F Mujica, ... ACM SIGCOMM Computer Communication Review 43 (4), 99-110, 2013 | 1407 | 2013 |
| Tiny Tera: a packet switch core N McKeown, M Izzard, A Mekkittikul, W Ellersick, M Horowitz IEEE micro 17 (1), 26-33, 1997 | 518 | 1997 |
| Self test of an electronic device RM Prentice, MJ Izzard US Patent 6,397,042, 2002 | 81 | 2002 |
| A 0.5-3.5 Gb/s low-power low-jitter serial data CMOS transceiver R Gu, JM Tran, HC Lin, AL Yee, M Izzard 1999 IEEE International Solid-State Circuits Conference. Digest of Technical …, 1999 | 50 | 1999 |
| Adaptive ocular projection display GN Nasserbakht, MJ Izzard US Patent 6,072,443, 2000 | 40 | 2000 |
| Distributed shared-memory packet switch JF Ren, RJ Landry, MJ Izzard US Patent 6,160,814, 2000 | 39 | 2000 |
| A 2 Gb/s asymmetric serial link for high-bandwidth packet switches KKY Chang, W Ellersick, ST Chuang, S Sidiropoulos, M Izzard, D Center Hot Interconnects V, Stanford University, 1-9, 1997 | 37 | 1997 |
| Priority encoder circuit MJ Izzard US Patent 6,170,032, 2001 | 20 | 2001 |
| Phase detector and method MJ Izzard, DB Scott US Patent 5,506,874, 1996 | 19 | 1996 |
| A unified circuit model for the polysilicon thin film transistor MJ Izzard, PMP Migliorato, WIMWI Milne Japanese journal of applied physics 30 (2A), L170, 1991 | 18 | 1991 |
| First-order loop control configuration for a phase-rotator based clock synchronization circuit MJ Izzard US Patent 5,526,380, 1996 | 17 | 1996 |
| Wireless chip-to-chip switching NC Warke, S Hosur, MJ Izzard, S Akhtar, BS Haroun, M Corsi US Patent 8,472,437, 2013 | 13 | 2013 |
| An integratable 1-2.5 gbps low jitter cmos transceiver with built in self test capability AL Yee, R Gu, A Tsong, R Prentice, J Tran, R Venett, S Spencer, V Pathak, ... 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No. 99CH36326 …, 1999 | 13 | 1999 |
| The Tiny Tera: A Packet Switch Core, Hot Interconnects V N McKeown, M Izzard, A Mekkittikul, B Ellersick, M Horowitz Stanford University, August, 1996 | 8 | 1996 |
| Analog Versus Digital Control of a Clock Synchronizer for 3 gb/s Data with 3. ov Differential Ecl MJ Izzard, CG Thisell, H Mader, M Hedberg, PK Fung, H Chang, ... Proceedings of 1994 IEEE Symposium on VLSI Circuits, 39-40, 1994 | 8 | 1994 |
| Modeling and Control of bittide Synchronization S Lall, C Caşcaval, M Izzard, T Spalink 2022 American Control Conference (ACC), 5185-5192, 2022 | 6 | 2022 |
| Logical Synchrony and the bittide Mechanism S Lall, C Cas, M Izzard, T Spalink IEEE Transactions on Parallel and Distributed Systems, 2024 | 5 | 2024 |
| Resistance distance and control performance for bittide synchronization S Lall, C Caşcaval, M Izzard, T Spalink 2022 European Control Conference (ECC), 1850-1857, 2022 | 5 | 2022 |
| A study of the host-network interface for MPEG based desktop video conferencing PN Anirudhan, HS Chang, MJ Izzard Proceedings of GLOBECOM'95 3, 1930-1936, 1995 | 5 | 1995 |
