| QMCPACK: an open source ab initio quantum Monte Carlo package for the electronic structure of atoms, molecules and solids J Kim, AD Baczewski, TD Beaudet, A Benali, MC Bennett, MA Berrill, ... Journal of Physics: Condensed Matter 30 (19), 195901, 2018 | 285 | 2018 |
| CosmoFlow: Using deep learning to learn the universe at scale A Mathuriya, D Bard, P Mendygral, L Meadows, J Arnemann, L Shao, ... SC18: International Conference for High Performance Computing, Networking …, 2018 | 129 | 2018 |
| Compute in memory circuits with multi-Vdd arrays and/or analog multipliers HE Sumbul, P Knag, GK Chen, R Kumar, A Sharma, S Manipatruni, ... US Patent 11,061,646, 2021 | 70 | 2021 |
| Artificial intelligence processor with three-dimensional stacked memory S Manipatruni, RK Dokania, A Mathuriya, R Ramesh US Patent 11,139,270, 2021 | 61 | 2021 |
| GTfold a scalable multicore code for RNA secondary structure prediction A Mathuriya, DA Bader, CE Heitsch, SC Harvey Proceedings of the 2009 ACM symposium on Applied Computing, 981-988, 2009 | 60 | 2009 |
| Artificial intelligence processor with three-dimensional stacked memory S Manipatruni, RK Dokania, A Mathuriya, R Ramesh US Patent 11,171,115, 2021 | 50 | 2021 |
| Integration method of ferroelectric memory array G Thareja, S Manipatruni, RK Dokania, R Ramesh, A Mathuriya US Patent 11,289,497, 2022 | 49 | 2022 |
| Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits A Sharma, JT Kavalieros, IA Young, S Manipatruni, R Krishnamurthy, ... US Patent 11,138,499, 2021 | 46 | 2021 |
| Ferroelectric capacitor and method of patterning such G Thareja, S Manipatruni, RK Dokania, R Ramesh, A Mathuriya US Patent 11,430,861, 2022 | 39 | 2022 |
| In-memory multiply and accumulate with global charge-sharing HE Sumbul, GK Chen, R Kumar, P Knag, A Sharma, S Manipatruni, ... US Patent 10,748,603, 2020 | 37 | 2020 |
| Low power ferroelectric based majority logic gate carry propagate and serial adder S Manipatruni, YS Fang, R Menezes, RK Dokania, G Thareja, R Ramesh, ... US Patent 11,283,453, 2022 | 36 | 2022 |
| Low power ferroelectric based majority logic gate adder S Manipatruni, YS Fang, R Menezes, RK Dokania, G Thareja, R Ramesh, ... US Patent 10,944,404, 2021 | 36 | 2021 |
| Pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic RK Dokania, A Mathuriya, S Manipatruni US Patent 11,482,270, 2022 | 34 | 2022 |
| Ferroelectric capacitor integrated with logic G Thareja, S Manipatruni, RK Dokania, R Ramesh, A Mathuriya US Patent 11,522,044, 2022 | 33 | 2022 |
| Method for using and forming low power ferroelectric based majority logic gate adder S Manipatruni, YS Fang, R Menezes, RK Dokania, G Thareja, R Ramesh, ... US Patent 11,502,691, 2022 | 32 | 2022 |
| Compute in memory circuits with time-to-digital computation R Kumar, P Knag, GK Chen, HE Sumbul, S Manipatruni, A Mathuriya, ... US Patent 11,048,434, 2021 | 29 | 2021 |
| Binary, ternary and bit serial compute-in-memory circuits P Knag, GK Chen, R Kumar, HE Sumbul, A Sharma, S Manipatruni, ... US Patent 10,642,922, 2020 | 29 | 2020 |
| Stacked ferroelectric non-planar capacitors in a memory bit-cell RK Dokania, N Sato, T Gosavi, P Pandey, D Olaosebikan, A Mathuriya, ... US Patent 11,423,967, 2022 | 26 | 2022 |
| 3D integrated ultra high-bandwidth memory RK Dokania, S Manipatruni, A Mathuriya, D Olaosebikan US Patent 11,043,472, 2021 | 25 | 2021 |
| TensorFlow at Scale: Performance and productivity analysis of distributed training with Horovod, MLSL, and Cray PE ML T Kurth, M Smorkalov, P Mendygral, S Sridharan, A Mathuriya Concurrency and Computation: Practice and Experience 31 (16), e4989, 2019 | 23 | 2019 |
Sasi ManipatruniKepler/Intel/Cornell在 cornell.edu 的电子邮件经过验证
