| Efficient Medical Image Enhancement Technique Using Transform HSV Space and Adaptive Histogram Equalization SS Bhairannawar Soft Computing Based Medical Image Analysis, Elsevier, 51-60, 2018 | 31 | 2018 |
| Design and Implementation of High Speed Background Subtraction Algorithm for Moving Object Detection SR Hanchinamani, S Sarkar, SS Bhairannawar 6th International Conference On Advances In Computing & Communications …, 2016 | 26 | 2016 |
| Color image enhancement using Laplacian filter and contrast limited adaptive histogram equalization S Bhairannawar, A Patil, A Janmane, M Huilgol IEEE, Power and Advanced Computing Technologies (i-PACT), 2017 Innovations …, 2017 | 23 | 2017 |
| Implementation of fingerprint based biometric system using optimized 5/3 DWT architecture and modified CORDIC based FFT SS Bhairannawar, S Sarkar, KB Raja, KR Venugopal Circuits, Systems, and Signal Processing, Springer 37 (1), 342-366, 2018 | 21 | 2018 |
| Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications S Sarkar, SS Bhairannawar Multidimensional Systems and Signal Processing 32 (2), 821-844, 2021 | 14 | 2021 |
| An efficient VLSI architecture for fingerprint recognition using O2D-DWT architecture and modified CORDIC-FFT SS Bhairannawar, S Sarkar, KB Raja, KR Venugopal 2015 IEEE International Conference on Signal Processing, Informatics …, 2015 | 13 | 2015 |
| A novel FPGA based reconfigurable architecture for image color space conversion MC Hanumantharaju, GR Vishalakshi, S Halvi, SB Satish Global Trends in Information Systems and Software Applications: 4th …, 2012 | 12 | 2012 |
| FPGA Implementation of Optimized Karhunen–Loeve Transform for Image Processing Applications SS Bhairannawar, S Sarkar, KB Raja Journal of Real-Time Image Processing, Springer, 1-14, 2018 | 11 | 2018 |
| FPGA IMPLEMENTATION OF MOVING OBJECT AND FACE DETECTION USING ADAPTIVE THRESHOLD Sateesh Kumar H.C., Sayantam Sarkar, Satish S Bhairannawar, Raja K.B ... International Journal of VLSI design & Communication Systems (VLSICS) 6 (5), 20, 2015 | 11* | 2015 |
| FPGACam: A FPGA based efficient camera interfacing architecture for real time video processing S Sarkar, SS Bhairannawar, R KB IET Circuits, Devices & Systems 15 (8), 814-829, 2021 | 10 | 2021 |
| FPGA implementation of face recognition system using efficient 5/3 2D-lifting scheme SS Bhairannawar, R Kumar, V Mirji, PS Sindhu IEEE, VLSI Systems, Architectures, Technology and Applications (VLSI-SATA …, 2016 | 9 | 2016 |
| AN EFFICIENT RECONFIGURABLE ARCHITECTURE FOR FINGERPRINT RECOGNITION SS Bhairannawar, KB Raja, KR Venugopal VLSI Design 2016, 22, 2016 | 6 | 2016 |
| FPGA based efficient Multiplier for Image Processing Applications using Recursive Error Free Mitchell Log Multiplier and KOM Architecture SS Bhairannawar, LM Patnaik arXiv preprint arXiv:1407.2082, 2014 | 6 | 2014 |
| FPGA based Recursive Error Free Mitchell Log Multiplier for image Filters SS Bhairannawar, R Rathan, KB Raja, KR Venugopal, LM Patnaik Computational Intelligence & Computing Research (ICCIC), 2012 IEEE …, 2012 | 6 | 2012 |
| Notice of Removal: FPGA Implementation of Fingerprint Recognition System using Adaptive Threshold Technique SS Bhairannawar, R Anand, KB Raja, KR Venugopal 2015 International Conference on Electrical, Electronics, Signals …, 2015 | 5 | 2015 |
| An Efficient VLSI Architecture for Adaptive Rank Order Filter for Image Noise Removal MC Hanumantharaju, M Ravishankar, DRR Babu, S Bhairannawar International journal for Information and Electronics Engineering 1 (1), 2011 | 5 | 2011 |
| Plant Leaf Disease Classification Using Modified SVM With Post Processing Techniques R Thyagaraj, TY Satheesha, S Bhairannawar 2023 International Conference on Applied Intelligence and Sustainable …, 2023 | 4 | 2023 |
| An Adaptive Threshold based FPGA Implementation for Object and Face Detection S Kumar, S Sayantam, SS Bhairannawar, KB Raja, V K R: IEEE Third International Conference on Image Information Processing, Shimla …, 2015 | 4 | 2015 |
| FPGA implementation of high speed Vedic multiplier using CSLA for parallel FIR architecture SA Naaz, MN Pradeep, S Bhairannawar, S Halvi 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS), 1-5, 2014 | 4 | 2014 |
| EEG Classification Using Modified KNN Algorithm BM Thejaswini, TY Satheesha, S Bhairannawar 2023 International Conference on Applied Intelligence and Sustainable …, 2023 | 3 | 2023 |
