| The TimberWolf placement and routing package C Sechen, A Sangiovanni-Vincentelli IEEE Journal of Solid-State Circuits 20 (2), 510-522, 1985 | 755 | 1985 |
| TimberWolf3. 2: A new standard cell placement and global routing package C Sechen, A Sangiovanni-Vincentelli 23rd ACM/IEEE Design Automation Conference, 432-439, 1986 | 346 | 1986 |
| VLSI placement and global routing using simulated annealing C Sechen Springer Science & Business Media, 2012 | 328 | 2012 |
| Efficient and effective placement for very large circuits WJ Sun, C Sechen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1995 | 312 | 1995 |
| Timing driven placement for large standard cell circuits W Swartz, C Sechen Proceedings of the 32nd Annual ACM/IEEE Design Automation Conference, 211-215, 1995 | 226 | 1995 |
| Toward an open-source digital flow: First learnings from the openroad project T Ajayi, VA Chhabria, M Fogaça, S Hashemi, A Hosny, AB Kahng, M Kim, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019 | 170 | 2019 |
| New algorithms for the placement and routing of macro cells W Swartz, C Sechen 1990 IEEE International Conference on Computer-Aided Design, 336,337,338,339 …, 1990 | 152 | 1990 |
| Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing C Sechen 25th ACM/IEEE, Design Automation Conference. Proceedings 1988., 73-80, 1988 | 137 | 1988 |
| A unified approach to the approximate symbolic analysis of large analog integrated circuits Q Yu, C Sechen IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 1996 | 131 | 1996 |
| Timing and crosstalk driven area routing HP Tseng, L Scheffer, C Sechen Proceedings of the 35th annual Design Automation Conference, 378-381, 1998 | 120 | 1998 |
| A new global router for row-based layout KW Lee, C Sechen [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89 …, 1988 | 111 | 1988 |
| Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step H Tennakoon, C Sechen Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002 | 101 | 2002 |
| A gridless multilayer router for standard cell circuits using CTM cells HP Tseng, C Sechen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999 | 82 | 1999 |
| An improved objective function for mincut circuit partitioning C Sechen, D Chen 1988 IEEE International Conference on Computer-Aided Design, 502,503,504,505 …, 1988 | 73 | 1988 |
| DC small signal symbolic analysis of large analog integrated circuits JJ Hsu, C Sechen IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 1994 | 68 | 1994 |
| Clock-delayed domino for adder and combinational logic design G Yee, C Sechen Proceedings International Conference on Computer Design. VLSI in Computers …, 1996 | 67 | 1996 |
| Clock-delayed domino for dynamic circuit design G Yee, C Sechen IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (4), 425-430, 2000 | 63 | 2000 |
| A MEMS-Assisted Temperature Sensor With 20- Resolution, Conversion Rate of 200 S/s, and FOM of 0.04 pJK2 MH Roshan, S Zaliasl, K Joo, K Souri, R Palwai, LW Chen, A Singh, ... IEEE Journal of Solid-State Circuits 52 (1), 185-197, 2016 | 60 | 2016 |
| The future of custom cell generation in physical synthesis M Lefebvre, D Marple, C Sechen Proceedings of the 34th annual Design Automation Conference, 446-451, 1997 | 56 | 1997 |
| Average interconnection length estimation for random and optimized placements C Sechen Proceedings IEEE International Conf. on Computer-Aided Design, 190-193, 1987 | 55 | 1987 |
