| The worst-case execution-time problem—overview of methods and survey of tools R Wilhelm, J Engblom, A Ermedahl, N Holsti, S Thesing, D Whalley, ... ACM Transactions on Embedded Computing Systems (TECS) 7 (3), 1-53, 2008 | 2721 | 2008 |
| Scheduling analysis of real-time systems with precise modeling of cache related preemption delay J Staschulat, S Schliecker, R Ernst 17th Euromicro Conference on Real-Time Systems (ECRTS'05), 41-48, 2005 | 160 | 2005 |
| Worst case timing analysis of input dependent data cache behavior J Staschulat, R Ernst 18th Euromicro Conference on Real-Time Systems (ECRTS'06), 10 pp.-236, 2006 | 63 | 2006 |
| Multiple process execution in cache related preemption delay analysis J Staschulat, R Ernst Proceedings of the 4th ACM international conference on Embedded software …, 2004 | 59 | 2004 |
| Scalable precision cache analysis for real-time software J Staschulat, R Ernst ACM Transactions on Embedded Computing Systems (TECS) 6 (4), 25-es, 2007 | 43 | 2007 |
| Micro-ros K Belsare, AC Rodriguez, PG Sánchez, J Hierro, T Kołcon, R Lange, ... Robot Operating System (ROS) The Complete Reference (Volume 7), 3-55, 2023 | 37 | 2023 |
| The rclc executor: Domain-specific deterministic scheduling mechanisms for ros applications on microcontrollers: work-in-progress J Staschulat, I Lütkebohle, R Lange 2020 International Conference on Embedded Software (EMSOFT), 18-19, 2020 | 37 | 2020 |
| Associative caches in formal software timing analysis F Wolf, J Staschulat, R Ernst Proceedings of the 39th annual Design Automation Conference, 622-627, 2002 | 28 | 2002 |
| Dataflow models for shared memory access latency analysis J Staschulat, M Bekooij Proceedings of the seventh ACM international conference on Embedded software …, 2009 | 26 | 2009 |
| Hybrid cache analysis in running time verification of embedded software F Wolf, J Staschulat, R Ernst Design Automation for Embedded Systems 7 (3), 271-295, 2002 | 21 | 2002 |
| Analysis of memory latencies in multi-processor systems J Stachulat, S Schliecker, M Ivers, R Ernst 5th International Workshop on Worst-Case Execution Time Analysis (WCET'05)(2007), 2007 | 20 | 2007 |
| Scalable precision cache analysis for preemptive scheduling J Staschulat, R Ernst Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages …, 2005 | 18 | 2005 |
| Combining robotics component-based model-driven development with a model-based performance analysis A Lotz, A Hamann, R Lange, C Heinzemann, J Staschulat, V Kesel, ... 2016 IEEE International Conference on Simulation, Modeling, and Programming …, 2016 | 17 | 2016 |
| Context sensitive performance analysis of automotive applications J Staschulat, R Ernst, A Schulze, F Wolf Design, Automation and Test in Europe, 165-170, 2005 | 17 | 2005 |
| Budget-based real-time executor for micro-ros J Staschulat, R Lange, DN Dasari arXiv preprint arXiv:2105.05590, 2021 | 10 | 2021 |
| A framework for the busy time calculation of multiple correlated events S Schliecker, M Ivers, J Staschulat, R Ernst 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06)(2006), 2006 | 8 | 2006 |
| Network mode switching method and serial data communication network AK Nieuwland, J Staschulat, EFM Steffens, HGH Vermeulen US Patent 8,817,659, 2014 | 6 | 2014 |
| Cost-efficient worst-case execution time analysis in industrial practice J Staschulat, JC Braam, R Ernst, T Rambow, R Schlor, R Busch Second International Symposium on Leveraging Applications of Formal Methods …, 2006 | 6 | 2006 |
| Instruction and data cache timing analysis in fixed-priority preemptive real-time systems J Staschulat Cuvillier Verlag, 2007 | 4 | 2007 |
| Cache effects in multi process real-time systems with preemptive scheduling J Staschulat, R Ernst Technical report, IDA, TU, 2003 | 4 | 2003 |
