| Automatic floating-point to fixed-point conversion for DSP code generation D Menard, D Chillet, F Charot, O Sentieys Proceedings of the 2002 international conference on Compilers, architecture …, 2002 | 104 | 2002 |
| Floating-to-fixed-point conversion for digital signal processors D Menard, D Chillet, O Sentieys EURASIP Journal on Advances in Signal Processing 2006, 1-19, 2006 | 102 | 2006 |
| DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints. R David, D Chillet, S Pillement, O Sentieys ipdps, 2002 | 85 | 2002 |
| UPaRC—Ultra-fast power-aware reconfiguration controller R Bonamy, HM Pham, S Pillement, D Chillet 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012 | 41 | 2012 |
| Flexible interconnection network for dynamically and partially reconfigurable architectures L Devaux, S Ben Sassi, S Pillement, D Chillet, D Demigny International Journal of Reconfigurable Computing 2010 (1), 390545, 2010 | 35 | 2010 |
| Power consumption model for partial and dynamic reconfiguration R Bonamy, D Chillet, S Bilavarn, O Sentieys 2012 International Conference on Reconfigurable Computing and FPGAs, 1-8, 2012 | 33 | 2012 |
| An efficient framework for power-aware design of heterogeneous MPSoC RB Atitallah, E Senn, D Chillet, M Lanoe, D Blouin IEEE Transactions on Industrial Informatics 9 (1), 487-501, 2012 | 33 | 2012 |
| Co-Design of Massively Parallel Embedded Processor Architectures. F Hannig, H Dutta, A Kupriyanov, J Teich, R Schaffer, S Siegel, R Merker, ... ReCoSoC, 27-34, 2005 | 31 | 2005 |
| Dart: A dynamically reconfigurable architecture dealing with next generation telecommunications constraints R David, D Chillet, S Pillement, O Sentieys 9th IEEE Reconfigurable Architecture Workshop RAW, 2002 | 29 | 2002 |
| Energy-efficient scheduling of real-time tasks in reconfigurable homogeneous multicore platforms A Gammoudi, A Benzina, M Khalgui, D Chillet IEEE Transactions on Systems, Man, and Cybernetics: Systems 50 (12), 5092-5105, 2018 | 26 | 2018 |
| Memory module selection for high level synthesis O Sentieys, D Chillet, JP Diguet, JL Philippe VLSI Signal Processing, IX, 273-282, 1996 | 25 | 1996 |
| Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC J Luo, A Elantably, VD Pham, C Killian, D Chillet, S Le Beux, O Sentieys, ... Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 23 | 2017 |
| Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network D Chillet, A Eiche, S Pillement, O Sentieys Journal of Systems Architecture 57 (4), 340-353, 2011 | 21 | 2011 |
| Considering reconfiguration overhead in scheduling of dependent tasks on 2D reconfigurable FPGA QH Khuat, D Chillet, M Hübner 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 1-8, 2014 | 20 | 2014 |
| Open-people: Open power and energy optimization PLatform and estimator E Senn, D Chillet, O Zendra, C Belleudy, SB Bilavarn, RB Atitallah, ... 2012 15th Euromicro Conference on Digital System Design, 668-675, 2012 | 20 | 2012 |
| OveRSoC: a framework for the exploration of RTOS for RSoC platforms B Miramond, E Huck, F Verdier, A Benkhelifa, B Granado, T Lefebvre, ... International Journal of Reconfigurable Computing 2009 (1), 450607, 2009 | 20 | 2009 |
| Approximate nanophotonic interconnects J Lee, C Killian, SL Beux, D Chillet Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip …, 2019 | 18 | 2019 |
| Power consumption models for the use of dynamic and partial reconfiguration R Bonamy, S Bilavarn, D Chillet, O Sentieys Microprocessors and Microsystems 38 (8), 860-872, 2014 | 18 | 2014 |
| A compilation framework for a dynamically reconfigurable architecture R David, D Chillet, S Pillement, O Sentieys Field-Programmable Logic and Applications: Reconfigurable Computing Is Going …, 2002 | 18 | 2002 |
| Task placement for dynamic and partial reconfigurable architecture A Eiche, D Chillet, S Pillement, O Sentieys 2010 Conference on Design and Architectures for Signal and Image Processing …, 2010 | 16 | 2010 |
