Circuit failure prediction and its application to transistor aging M Agarwal, BC Paul, M Zhang, S Mitra 25th IEEE VLSI Test Symposium (VTS'07), 277-286, 2007 | 610 | 2007 |
Robust subthreshold logic for ultra-low power operation H Soeleman, K Roy, BC Paul IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (1), 90-99, 2001 | 379 | 2001 |
Impact of NBTI on the temporal performance degradation of digital circuits BC Paul, K Kang, H Kufluoglu, MA Alam, K Roy IEEE Electron Device Letters 26 (8), 560-562, 2005 | 368 | 2005 |
A process-tolerant cache architecture for improved yield in nanoscale technologies A Agarwal, BC Paul, H Mahmoodi, A Datta, K Roy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (1), 27-38, 2005 | 266 | 2005 |
A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors GF Close, S Yasuda, B Paul, S Fujita, HSP Wong Nano Letters 8 (2), 706-709, 2008 | 253 | 2008 |
Modeling and optimization of fringe capacitance of nanoscale DGMOS devices A Bansal, BC Paul, K Roy IEEE Transactions on Electron Devices 52 (2), 256-262, 2005 | 228 | 2005 |
Process variation in embedded memories: failure analysis and variation aware architecture A Agarwal, BC Paul, S Mukhopadhyay, K Roy IEEE Journal of Solid-State Circuits 40 (9), 1804-1814, 2005 | 214 | 2005 |
Temporal performance degradation under NBTI: Estimation and design for improved reliability of nanoscale circuits BC Paul, K Kang, H Kufluoglu, MA Alam, K Roy Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 207 | 2006 |
Optimized circuit failure prediction for aging: Practicality and promise M Agarwal, V Balakrishnan, A Bhuyan, K Kim, BC Paul, W Wang, B Yang, ... 2008 IEEE International Test Conference, 1-10, 2008 | 195 | 2008 |
Novel sizing algorithm for yield improvement under process variation in nanometer technology SH Choi, BC Paul, K Roy Proceedings of the 41st annual Design Automation Conference, 454-459, 2004 | 189 | 2004 |
Fully integrated graphene and carbon nanotube interconnects for gigahertz high-speed CMOS electronics X Chen, D Akinwande, KJ Lee, GF Close, S Yasuda, BC Paul, S Fujita, ... IEEE Transactions on Electron Devices 57 (11), 3137-3143, 2010 | 182 | 2010 |
An analytical fringe capacitance model for interconnects using conformal mapping A Bansal, BC Paul, K Roy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 148 | 2006 |
Impact of a process variation on nanowire and nanotube device performance BC Paul, S Fujita, M Okajima, TH Lee, HSP Wong, Y Nishi IEEE Transactions on Electron Devices 54 (9), 2369-2376, 2007 | 140 | 2007 |
Contact engineering for organic semiconductor devices via Fermi level depinning at the metal-organic interface Z Liu, M Kobayashi, BC Paul, Z Bao, Y Nishi Physical Review B—Condensed Matter and Materials Physics 82 (3), 035311, 2010 | 133 | 2010 |
Device optimization for digital subthreshold logic operation BC Paul, A Raychowdhury, K Roy IEEE Transactions on Electron Devices 52 (2), 237-247, 2005 | 132 | 2005 |
Negative bias temperature instability: Estimation and design for improved reliability of nanoscale circuits BC Paul, K Kang, H Kufluoglu, MA Alam, K Roy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 102 | 2007 |
Low-power design techniques for scaled technologies BC Paul, A Agarwal, K Roy Integration 39 (2), 64-89, 2006 | 93 | 2006 |
Robust ultra-low power sub-threshold DTMOS logic H Soeleman, K Roy, B Paul Proceedings of the 2000 international symposium on Low power electronics and …, 2000 | 91 | 2000 |
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation A Raychowdhury, BC Paul, S Bhunia, K Roy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (11 …, 2005 | 82 | 2005 |
Modeling and analysis of circuit performance of ballistic CNFET BC Paul, S Fujita, M Okajima, T Lee Proceedings of the 43rd annual Design Automation Conference, 717-722, 2006 | 77 | 2006 |