| Taco: Timing analysis with coupling R Arunachalam, K Rajagopal, LT Pileggi Proceedings of the 37th Annual Design Automation Conference, 266-269, 2000 | 159 | 2000 |
| Determination of worst-case aggressor alignment for delay calculation PD Gross, R Arunachalam, K Rajagopal, LT Pileggi Proceedings of the 1998 IEEE/ACM international conference on Computer-aided …, 1998 | 154 | 1998 |
| Optimal shielding/spacing metrics for low power design R Arunachalam, E Acar, SR Nassif IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings., 167-172, 2003 | 116 | 2003 |
| CMOS gate delay models for general RLC loading R Arunachalam, F Dartu, LT Pileggi Proceedings International Conference on Computer Design VLSI in Computers …, 1997 | 80 | 1997 |
| False coupling interactions in static timing analysis R Arunachalam, RD Blanton, LT Pileggi Proceedings of the 38th annual Design Automation Conference, 726-731, 2001 | 46 | 2001 |
| Holistic risk-based identity establishment for eligibility determinations in context of an application N Alavandar, RS Arunachalam, DA Carlton, TM Corcoran, HT Kwan, ... US Patent 8,375,427, 2013 | 33 | 2013 |
| A novel algorithm for testing crosstalk induced delay faults in VLSI circuits R Arunachalam 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 33 | 2005 |
| Generation of refined switching windows in static timing analysis RJ Allen, R Arunachalam, DJ Hathaway US Patent 6,651,229, 2003 | 22 | 2003 |
| Predicting short circuit power from timing models E Acar, R Arunachalam, SR Nassif Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003 | 19 | 2003 |
| Water privatization and implications in india A Sampath, B Kedarnath, C Ramanujam, H Haidery, R Rao, ... Association for India’s Development, Austin USA, TX 78712, 2003 | 19 | 2003 |
| Generation of refined switching windows in static timing analysis RJ Allen, R Arunachalam, DJ Hathaway US Patent 6,988,255, 2006 | 16 | 2006 |
| Static transition probability analysis under uncertainty S Garg, S Tata, R Arunachalam IEEE International Conference on Computer Design: VLSI in Computers and …, 2004 | 8 | 2004 |
| Method and system for short-circuit current modeling in CMOS integrated circuits E Acar, R Arunachalam, SR Nassif US Patent 7,191,113, 2007 | 7 | 2007 |
| Timing Closure in DSM Design R Arunachalam, L Pileggi Integrated System Design 12, 50-57, 2000 | 3 | 2000 |
| ``Evaluation Method and Metrics of Shielding/Spacing Approaches for Coupling Avoidance,’’ R Arunachalam, E Acar, S Nassif research report, IBM Research Division, TJ Watson Research Center, Yorktown …, 2002 | 1 | 2002 |
| TACO: Timing Analysis with Coupling K Rajagopal, LT Pileggi, R Arunachalam Design Automation Conference, 266-269, 2000 | 1 | 2000 |
| Static timing analysis with coupling R Arunachalam Carnegie Mellon University, 2000 | 1 | 2000 |
| Implications in India RR Haidery, R Arunachalam, S Govindaraju Water Management: Concepts and Cases, 61, 2006 | | 2006 |
| Accurate coupling-centric timing analysis incorporating temporal and functional isolation R Arunachalam, RDS Blanton, LT Pileggi VLSI Design 15 (3), 605-618, 2002 | | 2002 |
| 1Determination of worstMcase aggressor alignment for delay calculation, 1 in Proc PD Gross, R Arunachalam, K Rajagopal, LT Pileggi Int. Conf. Comp. MAided Design (ICCAD), 212M219, 1998 | | 1998 |
