| A 550-10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction SH Cho, CK Lee, JK Kwon, ST Ryu IEEE Journal of Solid-State Circuits 46 (8), 1881-1892, 2011 | 158 | 2011 |
| 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme CK Lee, YJ Eom, JH Park, J Lee, HR Kim, K Kim, Y Choi, HJ Chang, J Kim, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 390-391, 2017 | 36 | 2017 |
| Memory device adjusting duty cycle and memory system having the same DS Moon, GH Cha, OH Ki-Seok, C Lee, C Yeon-Kyu, J Choi, KS Ha, ... US Patent 10,923,175, 2021 | 35 | 2021 |
| A two-channel asynchronous SAR ADC with metastable-then-set algorithm SH Cho, CK Lee, SG Lee, ST Ryu IEEE transactions on very large scale integration (VLSI) systems 20 (4), 765-769, 2011 | 33 | 2011 |
| A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration CK Lee, W Kim, JI Kim, HK Hong, GG Oh, CH Lee, M Choi, HJ Park, ... 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 281-284, 2013 | 30 | 2013 |
| A time-interleaved flash-SAR architecture for high speed A/D conversion BRS Sung, SH Cho, CK Lee, JI Kim, ST Ryu 2009 IEEE International Symposium on Circuits and Systems, 984-987, 2009 | 28 | 2009 |
| Memory modules, memory systems including the same, and methods of calibrating multi-die impedance of the memory modules JH Lee, C Lee, EOM Yoon-Joo US Patent 10,361,699, 2019 | 26 | 2019 |
| 23.1 a 7.5 Gb/s/pin LPDDR5 SDRAM with WCK clocking and non-target ODT for high speed and with DVFS, internal data copy, and deep-sleep mode for low power KS Ha, CK Lee, D Lee, D Moon, JH Jang, HR Hwang, H Chi, J Park, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 378-380, 2019 | 24 | 2019 |
| A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm … KC Chun, YG Chu, JS Heo, TS Kim, S Kim, HK Yang, MJ Kim, CK Lee, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 206-208, 2018 | 24 | 2018 |
| 22.2 An 8.5 Gb/s/pin 12Gb-LPDDR5 SDRAM with a hybrid-bank architecture using skew-tolerant, low-power and speed-boosting techniques in a 2nd generation 10nm DRAM process HJ Chi, CK Lee, J Park, JS Heo, J Jung, D Lee, DH Kim, D Park, K Kim, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 382-384, 2020 | 21 | 2020 |
| A replica-driving technique for high performance SC circuits and pipelined ADC design C Lee, W Kim, H Kang, ST Ryu IEEE Transactions on Circuits and Systems II: Express Briefs 60 (9), 557-561, 2013 | 20 | 2013 |
| Dual-loop two-step ZQ calibration for dynamic voltage–frequency scaling in LPDDR4 SDRAM CK Lee, J Lee, K Kim, JS Heo, JH Baek, GH Cha, D Moon, DH Lee, ... IEEE Journal of Solid-State Circuits 53 (10), 2906-2916, 2018 | 19 | 2018 |
| A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM with various high-speed and low-power techniques KS Ha, CK Lee, D Lee, D Moon, HR Hwang, D Park, YH Kim, YH Son, ... IEEE Journal of Solid-State Circuits 55 (1), 157-166, 2019 | 17 | 2019 |
| A 6.4 Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface CK Lee, M Ahn, D Moon, K Kim, YJ Eom, WY Lee, J Kim, S Yoon, B Choi, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), C182-C183, 2015 | 15 | 2015 |
| Design of a 1-Volt and μ-power SARADC for Sensor Network Application SH Cho, CK Lee, JI Song 2007 IEEE International Symposium on Circuits and Systems, 3852-3855, 2007 | 13 | 2007 |
| A 6-bit 3.3GS/s Current-Streering DAC with Stacked Unit Cell Structure CLSTR Si-Nai, Wan Kim Journal of Semiconductor Technology and Science 3, 270-277, 2012 | 12* | 2012 |
| A 10-bit 40-MS/s pipelined ADC with a wide range operating temperature for WAVE applications GG Oh, CK Lee, ST Ryu IEEE Transactions on Circuits and Systems II: Express Briefs 61 (1), 6-10, 2013 | 11 | 2013 |
| An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques CK Lee Journal of Solid-State Circuits, 2020 | 10 | 2020 |
| Memory modules, memory systems and methods of operating memory modules KIM Wang-Soo, J Choi, KD Park, YC Sung, JS Youn, C Lee, J Ju-Ho, ... US Patent 10,725,682, 2020 | 8 | 2020 |
| Digital error correction technique for binary decision successive approximation ADCs SH Cho, CK Lee, BRS Sung, ST Ryu Electronics letters 45 (8), 1, 2009 | 6 | 2009 |
Seung-Tak RyuKAIST, Korea在 kaist.ac.kr 的电子邮件经过验证
