A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking etc Y.-J Kim IEEE International Solid-State Circuit Conference (ISSCC), 2018., 0 | 56* | |
A 21-Gbit/s 1.63-pJ/bit adaptive CTLE and one-tap DFE with single loop spectrum balancing method YH Kim, YJ Kim, T Lee, LS Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (2), 789-793, 2015 | 42 | 2015 |
18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution HY Joo, SJ Bae, YS Sohn, YS Kim, KS Ha, MS Ahn, YJ Kim, YJ Kim, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 314-315, 2016 | 26 | 2016 |
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm … KC Chun, YG Chu, JS Heo, TS Kim, S Kim, HK Yang, MJ Kim, CK Lee, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 206-208, 2018 | 24 | 2018 |
An 8Gb/s 0.65 mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme JH Seol, YJ Kim, SH Chung, KS Ha, SJ Bae, JB Lee, JS Choi, LS Kim 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 15 | 2013 |
A 10-Gb/s 0.71-pJ/bit forwarded-clock receiver tolerant to high-frequency jitter in 65-nm CMOS SH Chung, YJ Kim, YH Kim, LS Kim IEEE Transactions on Circuits and Systems II: Express Briefs 63 (3), 264-268, 2015 | 11 | 2015 |
A 21%-jitter-improved self-aligned dividerless injection-locked PLL with a VCO control voltage ripple-compensated phase detector D Lee, T Lee, YJ Kim, LS Kim IEEE Transactions on Circuits and Systems II: Express Briefs 63 (8), 733-737, 2016 | 10 | 2016 |
A 12Gb/s 0.92 mW/Gb/s forwarded clock receiver based on ILO with 60MHz jitter tracking bandwidth variation using duty cycle adjuster in 65nm CMOS YJ Kim, LS Kim 2013 Symposium on VLSI Circuits, C236-C237, 2013 | 10 | 2013 |
An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider D Lee, T Lee, YH Kim, YJ Kim, LS Kim 2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015 | 9 | 2015 |
An 11.5 Gb/s 1/4th baud-rate CTLE and two-tap DFE with boosted high frequency gain in 110-nm CMOS YH Kim, YJ Kim, TH Lee, LS Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (3), 588-592, 2014 | 9 | 2014 |
A 9.6 Gb/s 0.96 mW/Gb/s forwarded clock receiver with high jitter tolerance using mixing cell integrated injection-locked oscillator YJ Kim, SH Chung, KS Ha, SJ Bae, LS Kim IEEE Transactions on Circuits and Systems I: Regular Papers 62 (10), 2495-2503, 2015 | 7 | 2015 |
A quarter-rate forwarded clock receiver based on ILO with low jitter tracking bandwidth variation using phase shifting phenomenon in 65 nm CMOS YJ Kim, SH Chung, LS Kim IEEE Transactions on Circuits and Systems I: Regular Papers 61 (8), 2482-2490, 2014 | 7 | 2014 |
A 7.4 Gb/s forwarded clock receiver based on first-harmonic injection-locked oscillator using AC coupled clock multiplication unit in 0.13 µm CMOS YJ Kim, SH Chung, LS Kim 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011 | 2 | 2011 |
A forwarded-clock receiver with constant and wide-range jitter-tracking bandwidth SH Chung, YJ Kim, KS Ha, SJ Bae, JB Lee, LS Kim IEEE Transactions on Circuits and Systems II: Express Briefs 61 (3), 153-157, 2014 | 1 | 2014 |
A 7 mW 2.5 GHz spread spectrum clock generator using switch-controlled injection-locked oscillator J Yang, YJ Kim, LS Kim 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 1392-1395, 2013 | 1 | 2013 |
Crosstalk avoidance code for direct pass-through architecture M Kim, S Chae, YJ Kim, SJ Bae, LS Kim 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2475-2478, 2016 | | 2016 |
A Forwarded Clock Receiver Based on Injection-Locked Oscillator With AC-Coupled Clock Multiplication Unit in m CMOS YJ Kim, SH Chung, LS Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (5), 988-992, 2014 | | 2014 |