| A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation TY Oh, H Chung, JY Park, KW Lee, S Oh, SY Doo, HJ Kim, CY Lee, ... IEEE Journal of Solid-State Circuits 50 (1), 178-190, 2015 | 115 | 2015 |
| A 1.2 V 30nm 1.6 Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme YC Bae, JY Park, SJ Rhee, SB Ko, Y Jeong, KS Noh, Y Son, J Youn, ... Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 …, 2012 | 47 | 2012 |
| 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme CK Lee, YJ Eom, JH Park, J Lee, HR Kim, K Kim, Y Choi, HJ Chang, J Kim, ... Solid-State Circuits Conference (ISSCC), 2017 IEEE International, 390-391, 2017 | 34 | 2017 |
| Semiconductor memory device, memory controller and memory system having on die termination and on die termination controlling method JY Park US Patent 8,581,621, 2013 | 21 | 2013 |
| 23.4 An extremely low-standby-power 3.733 Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices HJ Kwon, E Seo, CY Lee, YH Seo, GH Han, HR Kim, JH Lee, MS Jang, ... Solid-State Circuits Conference (ISSCC), 2017 IEEE International, 394-395, 2017 | 18 | 2017 |
| On-die termination circuit, semiconductor memory device and memory system OH Ki-Seok, JY Park, YH Ahn, YC Bae, YG Jeong, JH Choi US Patent 8,928,349, 2015 | 18 | 2015 |
| Semiconductor memory device, a memory module including the same, and a memory system including the same KW Lee, SJ Bae, JY Park, YC Bae US Patent 9,608,631, 2017 | 17 | 2017 |
| A storage-and power-efficient range-matching TCAM for packet classification YD Kim, HS Ahn, JY Park, S Kim, DK Jeong Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical …, 2006 | 16 | 2006 |
| Input data alignment circuit and semiconductor device including the same DS Moon, SJ Bae, JY Park, EOM Yoon-Joo US Patent 9,183,902, 2015 | 15 | 2015 |
| A 6.4 Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface CK Lee, M Ahn, D Moon, K Kim, YJ Eom, WY Lee, J Kim, S Yoon, B Choi, ... VLSI Circuits (VLSI Circuits), 2015 Symposium on, C182-C183, 2015 | 15 | 2015 |
| A low-cost, leakage-insensitive semi-digital PLL with linear phase detection and FIR-embedded digital frequency acquisition R He, C Liu, X Yu, W Rhee, JY Park, C Kim, Z Wang Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian, 1-4, 2010 | 14 | 2010 |
| A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method Y Koo, JY Park, J Park, W Kim VLSI and CAD, 1999. ICVC'99. 6th International Conference on, 339-341, 1999 | 12 | 1999 |
| Self-calibrating transceiver for source synchronous clocking system with on-chip TDR and swing level control scheme YC Jang, JY Park, S Shin, H Choi, K Lee, B Woo, H Park, WS Kim, Y Choi, ... VLSI Circuits, 2009 Symposium on, 54-55, 2009 | 7 | 2009 |
| A high-speed memory interface circuit tolerant to PVT variations and channel noise JY Park, Y Koo, DK Jeong, W Kim, C Yoo, C Kim Solid-State Circuits Conference, 2001. ESSCIRC 2001. Proceedings of the 27th …, 2001 | 7 | 2001 |
| Input buffer circuit for transforming pseudo differential signals into full differential signals J Park, C Yoo, K Jung, WC Kim US Patent 6,456,122, 2002 | 6 | 2002 |
| Delay locked loop and method and electronic device including the same W Rhee, YU Xueyi, JY Park, W Zhihua US Patent 8,295,106, 2012 | 4 | 2012 |
| Buffer circuit robust to variation of reference voltage signal EOM Yoon-Joo, SJ Bae, DS Moon, JY Park, M Ahn US Patent 9,742,355, 2017 | 3 | 2017 |
| A semi-digital cascaded CDR with fast phase acquisition and adaptive resolution control X Yu, J Qiao, W Rhee, JY Park, K Lee, Z Wang VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on …, 2010 | 3 | 2010 |
| Printed circuit board having traces and ball grid array package including the same H Kang, S Kang, J Park, D Hwang, T Yoon US Patent 9,355,947, 2016 | | 2016 |
| Output circuit for implementing high speed data transmition M Ahn, S Bae, JY Park, EOM Yoon-Joo US Patent 9,355,706, 2016 | | 2016 |
