| Efficient hardware architectures for accelerating deep neural networks: Survey P Dhilleswararao, S Boppu, MS Manikandan, LR Cenkeramaddi IEEE access 10, 131788-131828, 2022 | 49 | 2022 |
| High SNM 32nm CNFET based 6T SRAM Cell design considering transistor ratio P Dhilleswararao, R Mahapatra, P Srinivas 2014 International Conference on Electronics and Communication Systems …, 2014 | 13 | 2014 |
| Methodology for Structured Data-Path Implementation in VLSI Physical Design: A Case Study D Pudi, SJ Harrison, D Stathis, S Boppu, A Hemani, LR Cenkeramaddi Electronics 11 (18), 2965, 2022 | 1 | 2022 |
| Design and implementation of optimized register file for streaming applications AK Patan, D Stathis, P Dhilleswararao, Y Yang, S Boppu, A Hemani 2021 25th International Symposium on VLSI Design and Test (VDAT), 1-4, 2021 | 1 | 2021 |
| Automating functional unit and register binding for synchoros CGRA platform D Pudi, U Tiwari, S Boppu, Y Yang, A Hemani Design Automation for Embedded Systems, 1-32, 2024 | | 2024 |
| Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures D Pudi, R Ryansh, V Goudu, S Boppu, A Hemani 2023 26th Euromicro Conference on Digital System Design (DSD), 16-23, 2023 | | 2023 |
| Implementation of Image Averaging on DRRA and DiMArch Architectures D Pudi, V Goudu, S Boppu, R Ratnu, A Hemani 2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems …, 2023 | | 2023 |
| Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures P Dhilleswararao, R Ryansh, S Boppu, Y Yang, A Hemani Proceedings of the 13th International Symposium on Highly Efficient …, 2023 | | 2023 |
| Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction AR Bommana, SU Siddamshetty, D Pudi, A Thumatti KR, S Boppu, ... ACM Transactions on Design Automation of Electronic Systems 28 (3), 1-35, 2023 | | 2023 |
