| Sparse reram engine: Joint exploration of activation and weight sparsity in compressed neural networks TH Yang, HY Cheng, CL Yang, IC Tseng, HW Hu, HS Chang, HP Li Proceedings of the 46th International Symposium on Computer Architecture …, 2019 | 189 | 2019 |
| Efficient and robust parallel dnn training through model parallelism on multi-gpu platform CC Chen, CL Yang, HY Cheng arXiv preprint arXiv:1809.02839, 2018 | 130 | 2018 |
| DL-RSIM: A simulation framework to enable reliable ReRAM-based accelerators for deep learning MY Lin, HY Cheng, WT Lin, TH Yang, IC Tseng, CL Yang, HW Hu, ... 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 76 | 2018 |
| Memory latency reduction via thread throttling HY Cheng, CH Lin, J Li, CL Yang 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 53-64, 2010 | 67 | 2010 |
| Core vs. uncore: The heart of darkness HY Cheng, J Zhan, J Zhao, Y Xie, J Sampson, MJ Irwin Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 46* | 2015 |
| Lap: Loop-block aware inclusion properties for energy-efficient asymmetric last level caches HY Cheng, J Zhao, J Sampson, MJ Irwin, A Jaleel, Y Lu, Y Xie ACM SIGARCH Computer Architecture News 44 (3), 103-114, 2016 | 34 | 2016 |
| Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell MF Chang, CH Chuang, YN Chiang, SS Sheu, CC Kuo, HY Cheng, ... 2016 IEEE international symposium on circuits and systems (ISCAS), 1142-1145, 2016 | 26 | 2016 |
| Improving GPGPU performance via cache locality aware thread block scheduling LJ Chen, HY Cheng, PH Wang, CL Yang IEEE Computer Architecture Letters 16 (2), 127-131, 2017 | 23 | 2017 |
| RePIM: Joint exploitation of activation and weight repetitions for in-ReRAM DNN acceleration CY Tsai, CF Nien, TC Yu, HY Yeh, HY Cheng 2021 58th ACM/IEEE Design Automation Conference (DAC), 589-594, 2021 | 17 | 2021 |
| EECache: Exploiting design choices in energy-efficient last-level caches for chip multiprocessors HY Cheng, M Poremba, N Shahidi, I Stalev, MJ Irwin, M Kandemir, ... Proceedings of the 2014 international symposium on Low power electronics and …, 2014 | 14 | 2014 |
| LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling ZL Ke, HY Cheng, CL Yang arXiv preprint arXiv:1810.04509, 2018 | 13 | 2018 |
| TAP: Reducing the energy of asymmetric hybrid last-level cache via thrashing aware placement and migration JY Luo, HY Cheng, C Lin, DW Chang IEEE Transactions on Computers 68 (12), 1704-1719, 2019 | 11 | 2019 |
| Dl-rsim: A reliability and deployment strategy simulation framework for reram-based cnn accelerators WT Lin, HY Cheng, CL Yang, MY Lin, K Lien, HW Hu, HS Chang, HP Li, ... ACM Transactions on Embedded Computing Systems (TECS) 21 (3), 1-29, 2022 | 9 | 2022 |
| Future computing platform design: A cross-layer design approach HY Cheng, C Hakert, KH Chen, YH Chang, JJ Chen, CL Yang, TW Kuo 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 312-317, 2021 | 9 | 2021 |
| EECache: A comprehensive study on the architectural design for energy-efficient last-level caches in chip multiprocessors HY Cheng, M Poremba, N Shahidi, I Stalev, MJ Irwin, M Kandemir, ... ACM Transactions on Architecture and Code Optimization (TACO) 12 (2), 1-22, 2015 | 9 | 2015 |
| An analytical model to exploit memory task scheduling HY Cheng, J Li, CL Yang Proceedings of the 2010 Workshop on Interaction between Compilers and …, 2010 | 9 | 2010 |
| Efficient bad block management with cluster similarity JN Yen, YC Hsieh, CY Chen, TY Chen, CL Yang, HY Cheng, Y Luo 2022 IEEE International Symposium on High-Performance Computer Architecture …, 2022 | 6 | 2022 |
| Analyzing opencl 2.0 workloads using a heterogeneous cpu-gpu simulator L Wang, RW Tsai, SC Wang, KC Chen, PH Wang, HY Cheng, YC Lee, ... 2017 IEEE International Symposium on Performance Analysis of Systems and …, 2017 | 6 | 2017 |
| GraphRSim: A joint device-algorithm reliability analysis for reram-based graph processing CF Nien, YJ Hsiao, HY Cheng, CY Wen, YC Ko, CC Lin 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 5 | 2020 |
| Adaptive burst-writes (abw) memory requests scheduling to reduce write-induced interference HY Cheng, MJ Irwin, Y Xie ACM Transactions on Design Automation of Electronic Systems (TODAES) 21 (1 …, 2015 | 4 | 2015 |
