| A FeFET based super-low-power ultra-fast embedded NVM technology for 22nm FDSOI and beyond S Dünkel, M Trentzsch, R Richter, P Moll, C Fuchs, O Gehring, M Majer, ... 2017 IEEE International Electron Devices Meeting (IEDM), 19.7. 1-19.7. 4, 2017 | 498 | 2017 |
| Field effect transistor having an interlayer dielectric material having increased intrinsic stress J Hohage, M Finken, C Streck, R Richter US Patent App. 11/873,547, 2008 | 457 | 2008 |
| Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device K Frohberg, V Grimm, S Mueller, M Lehr, R Richter, J Klais, M Mazur, ... US Patent 7,550,396, 2009 | 447 | 2009 |
| A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs M Trentzsch, S Flachowsky, R Richter, J Paul, B Reimer, D Utess, ... 2016 IEEE International Electron Devices Meeting (IEDM), 11.5. 1-11.5. 4, 2016 | 391 | 2016 |
| Nonvolatile field programmable spin-logic for reconfigurable computing R Richter, L Bär, J Wecker, G Reiss Applied physics letters 80 (7), 1291-1293, 2002 | 73 | 2002 |
| Semiconductor structure including a transistor having a layer of a stress-creating material and method for the formation thereof R Richter, J Hoentschel, P Javorka US Patent App. 14/167,001, 2014 | 44 | 2014 |
| Field programmable spin-logic based on magnetic tunnelling elements R Richter, H Boeve, L Bär, J Bangert, UK Klostermann, J Wecker, G Reiss Journal of magnetism and magnetic materials 240 (1-3), 127-129, 2002 | 44 | 2002 |
| Programmable logic elements and methods of operating the same R Richter, S Duenkel, S Beyer US Patent 10,033,383, 2018 | 43 | 2018 |
| Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device R Richter, A Wei, M Horstmann, J Hohage US Patent 7,906,383, 2011 | 29 | 2011 |
| Sidewall protection layer J Boemmels, F Feustel, R Richter US Patent App. 12/056,356, 2009 | 27 | 2009 |
| 2017 IEEE Int. Electron Devices Meeting (IEDM) S Dünkel, M Trentzsch, R Richter, P Moll, C Fuchs, O Gehring, M Majer, ... IEEE, 2017 | 23 | 2017 |
| Semiconductor device comprising a contact structure with increased etch selectivity R Richter, C Peters, H Salz, M Schaller US Patent 7,678,690, 2010 | 21 | 2010 |
| Field programmable spin-logic realized with tunnelling-magnetoresistance devices R Richter, H Boeve, L Bär, J Bangert, G Rupp, G Reiss, J Wecker Solid-State Electronics 46 (5), 639-643, 2002 | 21 | 2002 |
| Method of forming a semiconductor device structure and such a semiconductor device structure J Hoentschel, S Flachowsky, R Richter, P Javorka US Patent 9,472,642, 2016 | 20 | 2016 |
| Multi-gate FETs having corrugated semiconductor stacks and method of forming the same S Flachowsky, J Hoentschel, R Richter, P Javorka US Patent 9,391,176, 2016 | 20 | 2016 |
| Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby J Hoentschel, S Flachowsky, N Sassiat, R Richter US Patent 9,231,045, 2016 | 20 | 2016 |
| Cold temperature control in a semiconductor device A Mowry, C Scott, M Wiatr, R Richter US Patent 8,212,184, 2012 | 20 | 2012 |
| Technique for enhancing transistor performance by transistor specific contact design M Gerhardt, R Richter, T Feudel, U Griebenow US Patent 7,964,970, 2011 | 20 | 2011 |
| Method for reducing resist poisoning during patterning of stressed nitrogen-containing layers in a semiconductor device K Frohberg, R Richter, T Werner US Patent 7,871,941, 2011 | 20 | 2011 |
| Contact geometry having a gate silicon length decoupled from a transistor length R Richter, P Javorka, J Hoentschel, S Flachowsky US Patent 9,412,859, 2016 | 19 | 2016 |
