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Clara Nieto Taladriz
Clara Nieto Taladriz
Ph.D. Researcher, KU Leuven
在 kuleuven.be 的电子邮件经过验证 - 首页
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Dealing with the energy versus performance tradeoff in future CMOS digital circuit design
W Dehaene, R Uytterhoeven, C Nieto Taladriz Moreno, B Vanhoof
NANO-CHIPS 2030: On-Chip AI for an Efficient Data-Driven World, 89-115, 2020
22020
Automated In-Situ Monitoring for Variability-Resilient and Energy-Efficient Digital Circuits Demonstrated on a Viterbi Decoder in 22-nm CMOS
CN Taladriz, W Dehaene
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (9 …, 2023
12023
Activity and variability resilient in-situ timing monitoring for complex ultra-low voltage digital ICs
CN Taladriz, W Dehaene
2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 617-620, 2024
2024
Towards Efficient BLE Mesh: Design of an Autonomous Network Joining Algorithm
C Nieto-Taladriz, Y Murillo, S Pollin
arXiv preprint arXiv:1907.08419, 2019
2019
Towards efficient and self-sustaining BLE Mesh: design and implementation of an autonomous network joining algorithm= Diseño e implementación de un algoritmo de construcción de …
C Nieto-Taladriz Moreno
Telecomunicacion, 2018
2018
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