| ALIGN: A system for automating analog layout T Dhar, K Kunal, Y Li, M Madhusudan, J Poojary, AK Sharma, W Xu, ... IEEE Design & Test 38 (2), 8-18, 2020 | 51 | 2020 |
| Common-centroid layouts for analog circuits: Advantages and limitations AK Sharma, M Madhusudan, SM Burns, P Mukherjee, S Yaldiz, R Harjani, ... 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 29 | 2021 |
| Mining message flows from system-on-chip execution traces MR Ahmed, H Zheng, P Mukherjee, MC Ketkar, J Yang 2021 22nd international symposium on quality electronic design (ISQED), 374-380, 2021 | 13 | 2021 |
| Performance-aware common-centroid placement and routing of transistor arrays in analog circuits AK Sharma, M Madhusudan, SM Burns, S Yaldiz, P Mukherjee, R Harjani, ... 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 10 | 2021 |
| Mining message flows using recurrent neural networks for system-on-chip designs Y Cao, P Mukherjee, M Ketkar, J Yang, H Zheng 2020 21st International Symposium on Quality Electronic Design (ISQED), 389-394, 2020 | 10 | 2020 |
| Model synthesis for communication traces of system designs H Zheng, MR Ahmed, P Mukherjee, MC Ketkar, J Yang 2021 IEEE 39th International Conference on Computer Design (ICCD), 492-499, 2021 | 7 | 2021 |
| The ALIGN open-source analog layout generator: V1. 0 and beyond T Dhar, K Kunal, Y Li, Y Lin, M Madhusudan, J Poojary, AK Sharma, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-2, 2020 | 7 | 2020 |
| Efficient identification of unstable loops in large linear analog integrated circuits P Mukherjee, GP Fang, R Burt, P Li IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 5 | 2012 |
| A digital LDO in 22nm CMOS with a 4b self-triggered binary search windowed flash ADC featuring automatic analog layout generator framework X Liu, S Yaldiz, P Mukherjee, S Burns, H Krishnamurthy, K Ravichandran, ... 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2-4, 2022 | 4 | 2022 |
| Machine Learning for Analog Layout SM Burns, H Chen, T Dhar, R Harjani, J Hu, N Karmokar, K Kunal, Y Li, ... Machine Learning Applications in Electronic Design Automation, 505-544, 2022 | 4 | 2022 |
| Leveraging pre-silicon data to diagnose out-of-specification failures in mixed-signal circuits P Mukherjee, P Li Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 4 | 2014 |
| Approximate property checking of mixed-signal circuits P Mukherjee, CS Amin, P Li Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 4 | 2014 |
| Automatic stability checking for large linear analog integrated circuits P Mukherjee, GP Fang, R Burt, P Li Proceedings of the 48th Design Automation Conference, 304-309, 2011 | 3 | 2011 |
| Mining patterns from concurrent execution traces MR Ahmed, H Zheng, P Mukherjee, MC Ketkar, J Yang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 2 | 2021 |
| A comparative study of specification mining methods for soc communication traces MR Ahmed, H Zheng, P Mukherjee, MC Ketkar, J Yang 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 31-36, 2021 | 2 | 2021 |
| Using Presilicon Knowledge to Excite Nonlinear Failure Modes in Large Mixed-Signal Circuits P Mukherjee, P Li IEEE Design & Test 33 (5), 28-34, 2016 | 2 | 2016 |
| A Digital LDO in 22-nm CMOS With a 4-b Self-Triggered Binary Search Windowed Flash ADC Featuring Analog Layout Generator Framework X Liu, S Yaldiz, P Mukherjee, S Burns, H Krishnamurthy, K Ravichandran, ... IEEE Solid-State Circuits Letters 6, 101-104, 2023 | 1 | 2023 |
| Model synthesis for communication traces of system-on-chip designs H Zheng, MR Ahmed, P Mukherjee, MC Ketkar, J Yang arXiv preprint arXiv:2102.06989, 2021 | 1 | 2021 |
| Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients AK Sharma, M Madhusudan, SM Burns, S Yaldiz, P Mukherjee, R Harjani, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | | 2024 |
| Methods and apparatus to generate a surrogate model based on traces from a computing unit JS Turek, M Capotã, P Mukherjee, R Antonello US Patent App. 17/559,755, 2022 | | 2022 |
