| High-performance computing-in-memory architecture using STT-/SOT-based series triple-level cell MRAM V Nehra, S Prajapati, TN Kumar, BK Kaushik IEEE Transactions on Magnetics 57 (8), 1-12, 2021 | 15 | 2021 |
| Energy-efficient differential spin hall MRAM-based 4-2 magnetic compressor V Nehra, S Prajapati, P Tankwal, Z Zilic, TN Kumar, BK Kaushik IEEE Transactions on Magnetics 56 (1), 1-11, 2019 | 13 | 2019 |
| Performance comparison of single level STT and SOT MRAM cells for cache applications A Sura, V Nehra 2021 25th International Symposium on VLSI Design and Test (VDAT), 1-4, 2021 | 7 | 2021 |
| Simulation & Analysis of 8T SRAM Cell’s Stability at Deep Sub-Micron CMOS Technology for Multimedia Applications V Nehra, R Singh, NK Shukla, S Birla, M Kumar, A Goel Canadian Journal on Electrical and Electronics Engineering 3 (1), 11-16, 2012 | 6 | 2012 |
| Investigation of field-free switching of 2-D material-based spin–orbit torque magnetic tunnel junction M Shashidhara, V Nehra, S Srivatsava, S Panwar, A Acharya IEEE Transactions on Electron Devices 70 (3), 1430-1435, 2023 | 5 | 2023 |
| High-performance computing-in-memory architecture based on single-level and multilevel cell differential spin Hall MRAM S Prajapati, V Nehra, BK Kaushik IEEE Transactions on Magnetics 57 (9), 1-15, 2021 | 5 | 2021 |
| Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates P Tankwal, V Nehra, S Prajapati, BK Kaushik Circuit world 45 (4), 300-310, 2019 | 4 | 2019 |
| Network on chip: topologies, routing, implementation R Kamal, P Goyal, V Nehra Network 4 (1), 2012 | 4 | 2012 |
| Few-Layer Si and WS2-Based Surface Plasmon Resonance Sensor for Water Salinity Concentration Detection: Theoretical Insight K Singh, R Kumar, P Kumar, V Nehra, RK Gupta, M Yusuf Plasmonics, 1-11, 2024 | 3 | 2024 |
| Low energy and write-efficient spin-orbit torque-based triple-level cell MRAM S Dhull, A Nisar, V Nehra, S Prajapati, TN Kumar, BK Kaushik IEEE Transactions on Magnetics 59 (7), 1-8, 2023 | 2 | 2023 |
| Comparative analysis of logic gates based on spin transfer torque (STT) and differential spin hall effect (DSHE) switching mechanisms P Tankwal, V Nehra, BK Kaushik International Symposium on VLSI Design and Test, 428-441, 2019 | 2 | 2019 |
| Leakage Power Reduction Technique In Cmos Circuit: A State-Of-The-Art Review H Asija, V Nehra, PK Dahiya IOSR Journal of VLSI and Signal Processing 5 (4), 31-36, 2015 | 2 | 2015 |
| Differential spin Hall MRAM based low power logic circuits and multipliers V Nehra, S Prajapati, TN Kumar, BK Kaushik Semiconductor Science and Technology 37 (7), 075007, 2022 | 1 | 2022 |
| Spintronics Memory and Logic: An Efficient Alternative to CMOS Technology V Nehra, BK Kaushik VLSI and Post-CMOS Electronics Volume 1, Design, Modelling, and Simulations …, 2019 | 1 | 2019 |
| Time-domain finite-difference based analysis of induced crosstalk in multiwall carbon nanotube interconnects A Kumar, V Nehra, BK Kaushik Nanoengineering: Fabrication, Properties, Optics, and Devices XIV 10354, 120-127, 2017 | 1 | 2017 |
| Modeling and simulation analysis of graphene integrated silicon waveguides S Joshi, V Nehra, BK Kaushik Active Photonic Platforms IX 10345, 42-50, 2017 | 1 | 2017 |
| Impact of Unconventional Torque on the Performance of Weyl-Semimetal-Based SOT-MTJ: A Micromagnetic Study M Shashidhara, S Srivatsava, S Panwar, V Nehra, R Kamal, A Acharya IEEE Transactions on Electron Devices, 2024 | | 2024 |
Brajesh Kumar KaushikProfessor of Electronics and Communication Engg., IIT-Roorkee在 iitr.ac.in 的电子邮件经过验证
