| TCAD performance analysis of a symmetrical double gate non-aligned junction FET device with high and low dielectric gate oxide in sub-100 nm regime VB Naik, AK Sinha International Journal of Electronics Letters 11 (4), 399-410, 2023 | 5 | 2023 |
| A Proposed Nonaligned Double Gate Junction FET Device and its Performance Improvement Using High- Gate Oxide Material AK Sinha, BV Naik Nano 18 (06), 2350040, 2023 | 5 | 2023 |
| Effects of metal work function and gate-oxide dielectric on super high frequency performance of a non-align junction DG-MOSFET based inverter in the sub-100 nm … BV Naik, AK Sinha International Journal of Electronics 111 (9), 1441-1458, 2024 | 4 | 2024 |
| Nano Design of a Symmetrical Junction Non-Aligned Double Gate FET Device with Improved Analog Figure of Merit BV Naik, AK Sinha 2022 International Conference on Microelectronics (ICM), 213-216, 2022 | 4 | 2022 |
| RF and Linearity Analysis of a Symmetrical Junction Non-Aligned Double Gate FET Device BV Naik, AK Sinha 2022 International Conference on Microelectronics (ICM), 217-220, 2022 | 2 | 2022 |
| Design and implementation floating point multiplier design using combined booth and dadda algorithms K Nagalexmi, B Vasu Naik Int. J. VLSI Syst. Commun. Syst 3 (04), 2015 | 2 | 2015 |
| Evaluating Performance Using kϕ Index Parameter for a Symmetrical Junction NADGFET: A 3D TCAD Simulation Analysis AK Sinha, BV Naik 2023 International Conference on Next Generation Electronics (NEleX), 1-5, 2023 | 1 | 2023 |
| A 3D TCAD Model of a Non-aligned Double Gate Symmetrical Junction FET in Nanoscale Regime BV Naik, AK Sinha NanoWorld J 9 (S5), S23-S28, 2023 | | 2023 |
| Design and Analysis of Low Power Pulse Triggered Flip-Flop Based on Single Feed-Through Scheme M YASMEEN, BV NAIK | | 2015 |
| Design and Implementation of AES Algorithm with UART H NOWSHEEN, N BVasu | | 2014 |
| High Speed Fir Filter Designs Based on Faithfully Rounded Truncated Constant Multiplication/Accumulation A DEVI, BV NAIK | | 2014 |
| Paper id-3768 MBV Naik | | |
